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ksz9031rnx gigabit ethernet transceiver with rgmii support data sheet rev. 1.0 linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 ( 408 ) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com october 2012 m9999 -103112 -1 . 0 general description the ksz9031 r nx is a completely integrated triple - speed (10base - t/1 00base - tx/1000base - t) ethernet physical - layer t ransceiver for transmission and reception of data on standard cat - 5 unshielded twisted pair (utp) cable. the ksz9031rnx pr ovides the reduced gigabit media independent interface (rgmii) for direct connection to rgmii macs in gigabit ethernet processors and switches for data transfer at 10/100/1000mbps. the ksz9031 r nx reduces board cost and simplifies board layout by using on - c hip termination resistors for the four differential pairs and by integrating a n ldo controller to drive a low - cost mosfet to supply the 1.2v core. the ksz9031r nx offers diagnostic features to facilitate system bring - up and debugging in production testing a nd in product deployment. parametric nand tree support enables fault detection between ksz9031 i/os and the board. the linkmd ? tdr - based cable diagnostic identifies faulty copper cabling. remote and local loopback functions verify analog and digital data p aths. the ksz9031 r nx is available in a 48 - pin, lead - free qfn package (s ee ? ordering information ? ). data sheets and support documentation are available on micrel?s web site at: www.micr el.com . features ? single - chip 10/100/1000mbps ieee 802.3 compliant ethernet t ransceiver ? rgmii timing supports on - chip delay according to rgmii version 2.0, with programming options for external delay and making adjustments and corrections to tx and rx tim ing paths ? rgmii with 3.3v/2.5v/1.8v tolerant i/os ? auto - n egotiation to automatically select the highest link - up speed (10/100/100 0 mbps) and duplex (half/full) ? on - chip termination resistors for the differential pairs ? on - chip ldo controller to support single 3.3v supply operation ? requires only one external fet to generate 1.2v for the core ? jumbo frame support up to 16kb ? 125mhz reference c lock o utput ? energy d etect power - down m ode for reduced power consumption when the cable is not attached ? energy e fficient ethern et (eee) support with low - power i dle (lpi) mode and clock stoppage for 100base - tx/ 1000base - t and transmit amplitude reduction with 10base - te option ? wake - o n - lan ( wol) support with robust custom - packet detection functional diagram
micrel, inc. ksz9031rnx octobe r 2012 2 m9999 - 10 31 12 - 1.0 features (continued) ? programmable led outputs for link, activity , and speed ? baseline wander c orrection ? linkmd tdr - bas ed cable diagnostic to identify faulty copper cabling ? parametric nand t ree support to detect fault s between chip i/os and board ? loopback modes for diagnostics ? automatic mdi/mdi - x crossover to detect and correct pair swap at all speeds of operation ? automatic detection and correction of pair swaps, pair skew , and pair polarity ? mdc/mdio management i nterface for phy register configuration ? interrupt pin option ? power - down and power - saving modes ? operating v oltages ? core (dvddl, avddl, avddl_pll): 1.2v (external fet or regulator) ? vdd i/o (dvddh): 3.3v, 2.5v, or 1.8v ? transceiver (avddh): 3.3v or 2.5v (commercial temp) ? available in a 48- pin qfn (7mm x 7 mm) pack age applications ? laser/network p rinter ? network a ttached s torage (nas) ? network s erver ? gigabit lan on motherboard (glom) ? broadband g ateway ? gigabit soho/smb r outer ? iptv ? ip set - top b ox ? game c onsole ? triple - play (data, voice, video) media c enter ? media c onverter ordering information part number temperature range package lead finish wire bonding description ksz9031rnxca 0c to 70c 48- pin qfn pb - free gold rgmii, commercial temperature, gold wire bonding ksz9031rnxcc (1) 0c to 70c 48- pin qfn pb - free copper rgm ii, commercial temperature, copper wire bonding ksz9031rnxia (1) ? 40c to 85c 48- pin qfn pb - free gold rgmii, industrial temperature, gold wire bonding KSZ9031RNXIC (1) ? 40c to 85c 48- pin qfn pb - free copper rgmii, industrial temperature, copper wire bond ing ksz9031rnx -eval 0c to 70c 48- pin qfn pb - free ksz9031rnx evaluation board (mounted with ksz9031rnx device in commercial temperature) note: 1. contact factory for lead time.
micrel, inc. ksz9031rnx octobe r 2012 3 m9999 - 10 31 12 - 1.0 revision history revision date summary of changes 1.0 10/ 31 /12 data she et created
micrel, inc. ksz9031rnx octobe r 2012 4 m9999 - 10 31 12 - 1.0 contents general description ................................................................................................................................................................ 1 features .................................................................................................................................................................................. 1 functional diagram ................................................................................................................................................................. 1 features (continued) .............................................................................................................................................................. 2 applications ............................................................................................................................................................................. 2 ordering information ............................................................................................................................................................... 2 revision history ...................................................................................................................................................................... 3 contents .................................................................................................................................................................................. 4 list of figures .......................................................................................................................................................................... 7 list of tables ........................................................................................................................................................................... 8 pin configu ration ..................................................................................................................................................................... 9 pin description ...................................................................................................................................................................... 10 strapping options ................................................................................................................................................................. 15 functional overview .............................................................................................................................................................. 16 functional description: 10base - t/100base - tx transceiver ................................................................................................ 17 100base - tx transmit .......................................................................................................................................................................... 17 100base - tx receive ........................................................................................................................................................................... 17 scrambler/de - scrambler (100base - tx only) ...................................................................................................................................... 17 10base - t transmit .............................................................................................................................................................................. 17 10base - t receive ............................................................................................................................................................................... 17 functional description: 1000base - t transceiver ................................................................................................................. 18 analog echo - cancellation circuit ........................................................................................................................................................ 18 automatic gain control (agc) ............................................................................................................................................................ 18 analog -to - digital converter (adc) ...................................................................................................................................................... 19 timing recovery circuit ...................................................................................................................................................................... 19 adaptive equalizer ............................................................................................................................................................................... 19 trellis encoder and decoder ............................................................................................................................................................... 19 functional description: 10/100/1000 transceiver features ................................................................................................. 19 auto mdi/mdi - x .................................................................................................................................................................................. 19 pair - swap, alignment, and polarity check .......................................................................................................................................... 20 wave shaping, slew - rate control, and partial response .................................................................................................................. 20 pll clock synthesizer ........................................................................................................................................................................ 20 auto - negotiation ................................................................................................................................................................... 20 rgmii interface ..................................................................................................................................................................... 22 rgmii signal definition ................................................................................................................................ ....................................... 23 rgmii signal diagram ......................................................................................................................................................................... 23 rgmii pad skew registers ................................................................................................................................................................. 23 rgmii in - band status ......................................................................................................................................................................... 27 mii management (miim) interface ......................................................................................................................................... 27 interrupt (int_n) ................................................................................................................................................................... 28
micrel, inc. ksz9031rnx octobe r 2012 5 m9999 - 10 31 12 - 1.0 led mode ............................................................................................................................................................................. 28 single - led mode ................................................................................................................................................................................ 28 tri - color dual - led mode ..................................................................................................................................................................... 28 loopback mode ..................................................................................................................................................................... 29 local (digital) loopback ...................................................................................................................................................................... 29 remote (analog) loopback ................................................................................................................................................................. 30 linkmd ? cable diagnostic .................................................................................................................................................... 31 nand tree support .............................................................................................................................................................. 31 power management .............................................................................................................................................................. 32 energy - detect power - down mode ...................................................................................................................................................... 32 software power - down mode ............................................................................................................................................................... 32 chip power - down mode ...................................................................................................................................................................... 32 energy efficient ethernet (eee) ............................................................................................................................................ 32 transmit direction control (mac -to - phy) ........................................................................................................................................... 33 receive direction control (phy -to - mac) ............................................................................................................................................ 34 registers associated with eee ........................................................................................................................................................... 36 wake - on - lan ....................................................................................................................................................................... 36 magic - packet detection ....................................................................................................................................................................... 36 customized - packet detection ............................................................................................................................................................. 36 link status change detect ion ............................................................................................................................................................. 37 typical current/power consumption .................................................................................................................................... 38 transceiver (3.3v), digital i/os (3.3v) ................................................................................................................................................. 38 transceiver (3.3v), digital i/os (1.8v) ................................................................................................................................................. 38 transceiver ( 2.5v), digital i/os (2.5v) ................................................................................................................................................. 39 transceiver (2.5v), digital i/os (1.8v) ................................................................................................................................................. 39 register map ......................................................................................................................................................................... 40 standard registers ............................................................................................................................................................... 42 ieee defined registers ? descriptio ns ............................................................................................................................................... 42 vendor - specific registers ? descriptions ........................................................................................................................................... 48 mmd registers ...................................................................................................................................................................... 52 mmd registers ? descriptions ............................................................................................................................................................ 53 absolute maximum ratings ( 1) ................................................................................................................................................ 62 operating ratings (2) .............................................................................................................................................................. 62 electrical characteristics (3) .................................................................................................................................................... 62 timing diagrams ................................................................................................................................................................... 65 rgmii timing ...................................................................................................................................................................................... 65 auto - negotiation timing ...................................................................................................................................................................... 66 mdc/mdio timing .............................................................................................................................................................................. 67 power - up/power - down/reset timing ................................................................................................................................................. 68 reset circuit .......................................................................................................................................................................... 69 reference circuits ? led strap - in pins ................................................................................................................................ 70 reference clock ? connection and selection ...................................................................................................................... 71 magnetic ? connection and selection .................................................................................................................................. 72
micrel, inc. ksz9031rnx octobe r 2012 6 m9999 - 10 31 12 - 1.0 recomme nded land pattern ................................................................................................................................................ 74 package information ............................................................................................................................................................. 75
micrel, inc. ksz9031rnx octobe r 2012 7 m9999 - 10 31 12 - 1.0 list of figures figure 1. ksz9031rnx block diagram ............................................................................................................................... 16 figure 2. ksz9031rnx 1000base - t transceiver block diagram ? single channel .......................................................... 18 figure 3. auto - negotiation flow chart ................................................................................................................................. 21 figure 4. ksz9031rnx rgmii interface ............................................................................................................................. 23 figure 5. local (digital) loopback ....................................................................................................................................... 29 figure 6. remote (analog) loopback .................................................................................................................................. 30 figure 7. lpi mode (refresh transmissions and quiet periods) ........................................................................................ 33 figure 8. lpi transition ? rgmii (1000mbps) transmit ...................................................................................................... 33 figure 9. lpi transition ? rgmii (100mbps) transmit ........................................................................................................ 34 figure 10. lpi transition ? rgmii (1000mbps) receive ..................................................................................................... 35 figure 11. lpi transition ? rgmii (100mbps) receive ....................................................................................................... 35 f igure 12. rgmii v2.0 specification (figure 3 ? multiplexing and timing diagram) ........................................................... 65 figure 13. auto - negotiation fast link pulse (flp) timing ................................................................................................. 66 figure 14. mdc/mdio timing .............................................................................................................................................. 67 figure 15. power - up/power - down/reset timing ................................................................................................................ 68 figure 16. recommended reset circuit .............................................................................................................................. 69 figure 17. rec ommended reset circuit for interfacing with cpu/fpga reset output ..................................................... 69 figure 18. reference circuits for led strapping pins ......................................................................................................... 70 figure 19. 25mhz crystal/oscillator reference clock connection ..................................................................................... 71 figure 20. typical gigabit magnetic interface circuit .......................................................................................................... 72 figure 21. recommended land pattern, 48 - pin (7mm x 7mm) qfn ................................................................................. 74
micrel, inc. ksz9031rnx octobe r 2012 8 m9999 - 10 31 12 - 1.0 list of tables table 1. mdi/mdi - x pin mapping ........................................................................................................................................ 19 table 2. auto - negotiation timers ........................................................................................................................................ 22 table 3. rgmii signal definition .......................................................................................................................................... 23 table 4. rgmii pad skew registers ................................................................................................................................... 24 table 5. absolute delay for 5 - bit pad skew setting ............................................................................................................ 25 table 6. absolute delay for 4 - bit pad skew setting ............................................................................................................ 26 table 7. rgmii in - band status ............................................................................................................................................ 27 table 8. mii management frame format for the ksz9031rnx ......................................................................................... 27 table 9. single - led mode ? pin definition .......................................................................................................................... 28 table 10. tri - color dual - led mode ? pin definition ............................................................................................................ 28 table 11. nand tree test pin order for ksz9031rnx ..................................................................................................... 31 table 12. typical current/power consumption ? transceiver (3.3v), digital i/os (3.3v) ................................................... 38 table 13. typical current/power consumption ? transceiver (3.3v), digital i/os (1.8v) ................................................... 38 table 1 4. typical current/power consumption ? transceiver (2.5v), digital i/os (2.5v) ................................................... 39 table 15. typical current/power consumption ? transceiver (2.5v), digital i/os (1.8v) ................................................... 39 table 16. standard registers supported by ksz9031rnx ................................................................................................ 40 table 17. mmd registers supported by ksz9031rnx ...................................................................................................... 41 table 18. portal registers (access to indirect mmd registers) .......................................................................................... 52 table 19. rgmii v2.0 specification (timi ng specifics from table 2) .................................................................................. 65 table 20. auto - negotiation fast link pulse (flp) timing parameters ............................................................................... 66 table 21. mdc/mdio timing parameters ........................................................................................................................... 67 table 22. power - up/power - down/reset timing parameters ............................................................................................. 68 table 23. reference crystal/clock selection criteria .......................................................................................................... 71 table 24. magnetics selection criteria ................................................................................................................................ 73 table 25. compatible single - port 10/100/1000 magnetics ................................................................................................. 73
micrel, inc. ksz9031rnx octobe r 2012 9 m9999 - 10 31 12 - 1.0 pin configuration 48- pin qfn (top view)
micrel, inc. ksz9031rnx octobe r 2012 10 m9999 - 10 31 12 - 1.0 pin description pin number pin name type (1) pin function 1 avddh p 3.3v/2.5v (commercial temp only) analog v dd 2 txrxp_a i/o media dependent interface[0], positive signal of differential pair 1000base -t m ode: txrxp_a corresponds to bi_da+ for md i configuration and bi_db+ for mdi - x configuration, respectively. 10base - t/100base- tx m ode: txrxp_a is the positive transmit signal (tx+) for mdi configuration and the positive receive signal (rx+) for mdi - x configuration, respectively. 3 txrxm_a i/o media dependent interface[0], negative signal of differential pair 1000base -t m ode: txrxm_a corresponds to bi_da ? for mdi conf iguration and bi_db ? for mdi -x configuration, respectively. 10base -t/ 100base - tx m ode: txrxm_a is the negative transmit signal (tx ? ) for mdi configuration and the negative receive signal (rx ? ) for mdi - x configuration, respectively. 4 avddl p 1.2v analog v dd 5 txrx p_b i/o media dependent interface[1], positive signal of differential pair 1000base -t m ode: txrxp_b corresponds to bi_db+ for mdi configuration and bi_da+ for mdi - x configuration, respectively. 10base -t /100base - tx m ode: txrxp_b is the positive receive sign al ( rx+) for mdi configuration and the positive transmit signal (tx+) for mdi - x configuration, respectively. 6 txrxm_b i/o media dependent interface[1], negative signal of differential pair 1000base -t m ode: txrxm_b corresponds to bi_db ? for md i configurat ion and bi_da ? for mdi - x configuration, respectively. 10base -t /100base - tx m ode: txrxm_b is the negative receive signal (rx ? ) for mdi configurati on and the negative transmit signal (tx ? ) for mdi - x configuration, respectively. 7 txrxp_c i/o media dependent interface[2], positive signal of differential pair 1000base - t mode: txrxp_c corresponds to bi_dc+ for mdi configuration and bi_dd+ for mdi - x configuration, respectively. 10base - t/100base- tx mode: txrxp_c is not used. 8 txrxm_c i/o media dependent interfac e[2], negative signal of differential pair 1000base - t mode: txrxm_c corresponds to bi_dc ? for mdi configuration and bi_dd ? for mdi - x configuration, respectively. 10base - t/100base- tx mode: txrxm_c is not used. 9 avddl p 1.2v analog v dd
micrel, inc. ksz9031rnx octobe r 2012 11 m9999 - 10 31 12 - 1.0 pin number pin name type (1) pin function 10 txrxp_d i/o medi a dependent interface[3], positive signal of differential pair 1000base - t mode: txrxp_d corresponds to bi_dd+ for mdi configuration and bi_dc+ for mdi - x configuration, respectively. 10base - t/100base- tx mode: txrxp_d is not used. 11 txrxm_d i/o media depen dent interface[3], negative signal of differential pair 1000base - t mode: txrxm_d corresponds to bi_dd ? for mdi configuration and bi_dc ? for mdi - x configuration, respectively. 10base - t/100base- tx mode: txrxm_d is not used. 1 2 avddh p 3.3v/2.5v (commercial temp only) analog v dd 13 nc ? no connect this pin is not bonded and can be connected to digital ground for footprint compatibility with the micrel ksz9021rn gigabit phy. 1 4 dvddl p 1.2v digital v dd 15 led2/ phyad1 i/o led output: programmable led2 outp ut config mode: the pull - up/pull - down value is latched as phyad[1] during power - up/reset. see the ? strapping options ? section for details. the led2 pin is programmed by the led_mode strapping option (pin 41), and is def ined as follows: single - led mode link pin state led definition link off h off link on (any speed) l on tri - color dual - led mode link/activity pin state led definition led2 led1 led2 led1 link off h h off off 1000 link / no activity l h on off 1000 l ink / activity (rx, tx) toggle h blinking off 100 link / no activity h l off on 100 link / activity (rx, tx) h toggle off blinking 10 link / no activity l l on on 10 link / activity (rx, tx) toggle toggle blinking blinking for tri - color dual - led mode , led2 works in conjunction with led1 (pin 17) to indicate 10mbps link and activity. 16 dvddh p 3.3v, 2.5v, or 1.8v digital v dd_i/o
micrel, inc. ksz9031rnx octobe r 2012 12 m9999 - 10 31 12 - 1.0 pin number pin name type (1) pin function 17 led1/ phyad0/ pme_n1 i/o led1 output: programmable led1 output config mode: the voltage on this pin is sampled and latched during the power - up/reset process to determine the value of phyad[0]. see the ? strapping options ? section for details. pme_n output: programmable pme_n output (pin option 1). this pin function requires an exter nal pull - up resistor to dvddh ( digital v dd_i/o ) in a range from 1.0k to 4.7k . w hen asserted low, this pin signals that a wol event has occurred. the led1 pin is programmed by the l ed_mode strapping option (pin 4 1 ) , and is defined as follows. single - le d mode activity pin state led definition no a ctivity h off activity (rx, tx) toggle blinking tri - color dual - led mode link/activity pin state led definition led2 led1 led2 led1 link off h h off off 1000 link / no activity l h on off 1000 link / act ivity (rx, tx) toggle h blinking off 100 link / no activity h l off on 100 link / activity (rx, tx) h toggle off blinking 10 link / no activity l l on on 10 link / activity (rx, tx) toggle toggle blinking blinking for tri - color dual - led mode, led1 wo rks in conjunction with led2 (pin 15 ) to indicate 10mbps link and activity. 18 dvddl p 1.2v digital v dd 19 txd0 i r gmii mode: rgmii t d0 (transmit data 0) input 20 txd1 i r gmii mode: r gmii td1 (transmit data 1) input \ 21 txd2 i r gmii mode: r gmii td2 (tr ansmit data 2) input 22 txd3 i r gmii mode: rgmii t d3 (transmit data 3) input 23 dvddl p 1.2v digital v dd 24 gtx_clk i rgmii mode: rgmii txc (transmit reference clock) input 25 tx_en i rgmii mode: rgmii tx_ctl (transmit control) input 26 dvddl p 1.2v d igital v dd 27 rxd3/ mode3 i/o rgmii mode: rgmii rd3 (receive data 3) output config mode: the pull - up/pull - down value is latched as mode3 during power - up/reset. see the ? strapping options ? section for details. 28 rxd2/ m ode2 i/o rgmii mode: rgmii rd2 (receive data 2) output config mode: the pull - up/pull - down value is latched as mode2 during power - up/reset. see the ? strapping options ? section for details. 29 vss gnd digital ground 30 dv ddl p 1.2v digital v dd
micrel, inc. ksz9031rnx octobe r 2012 13 m9999 - 10 31 12 - 1.0 pin number pin name type (1) pin function 31 rxd1/ mode1 i/o rgmii mode: rgmii rd1 (receive data 1) output config mode: the pull - up/pull - down value is latched as mode 1 during power - up/reset. see the ? strapping options ? section for details. 32 rxd0/ mode0 i/o rgmii mode: rgmii rd0 (receive data 0) output config mode: the pull - up/pull - down value is latched as mode0 during power - up/reset. see the ? strapping options ? section for details. 33 rx_dv/ clk125_en i/o rgmii mode: rgmii rx_ctl (receive control) output config mode: latched as clk125_ndo output enable during power - up/reset. see the ? strapping options ? section for details. 34 dvddh p 3.3v, 2.5v, or 1.8v digital v dd_i /o 35 rx_clk/ phyad2 i/o rgmii mode: rgmii rxc (receive reference clock) output config mode: the pull - up/pull - down value is latched as phyad[2] during power - up/reset. see the ? strapping options ? section for details. 36 m dc ipu management data clock input this pin is the input reference clock for mdio (pin 37). 37 mdio ipu/o management data input/output this pin is synchronous to mdc (pin 36) and requires an external pull - up resistor to dvddh ( digital v dd_i/o ) in a range from 1.0k to 4.7k . 38 int_n/ pme_n2 o interrupt output: programmable interrupt output, with register 1bh as the interrupt control/status register, for programming the interrupt conditions and reading the interrupt status. register 1fh, bit [14] sets the i nterrupt output to active low (default) or active high. pme_n output: programmable pme_n output (pin option 2). when asserted low, this pin signals that a wol event has occurred. for interrupt (when active low) and pme functions, this pin requires an exte rnal pull - up resistor to dvddh ( digital v dd_i/o ) in a range from 1.0k to 4.7k . 39 dvddl p 1.2v digital v dd 40 dvddh p 3.3v, 2.5v, or 1.8v digital v dd _i/o 41 clk125_ndo/ led_mode i/o 125mhz clock output this pin provides a 125mhz reference clock output option for use by the mac. config mode: the pull - up/pull - down value is latched as led_mode during power - up/reset. see the ? strapping options ? section for details. 42 reset_n ipu chip reset (active low) hardware pin configurations are strapped - in at the de- assertion (rising edge) of reset _n. see the ? strapping options ? section for more details. 43 ldo_o o on - chip 1.2v ldo controller output this pin drives the input gate of a p - channel mosfet to generate 1.2v for the chip?s core voltages. if the system pro vides 1.2v and this pin is not used, it can be left floating. 44 avddl_pll p 1.2v analog v dd for pll 45 xo o 25mhz crystal feedback this pin is a no connect if an oscillator or external clock source is used. 46 xi i crystal / oscillator/ external clock input 25mhz 50ppm tolerance 47 nc ? no connect this pin is not bonded and can b e connected to avddh power for footprint compatibility with the micrel ksz9021rn gigabit phy.
micrel, inc. ksz9031rnx octobe r 2012 14 m9999 - 10 31 12 - 1.0 pin number pin name type (1) pin function 48 iset i/o set the transmit output level connect a 12.1k 1% resistor to ground on this pin. paddle p_gnd gnd exposed paddle on bottom of chip connect p_gnd to ground. note: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. ipu = input with internal pull - up (see ? electrical characteristics ? for value). ipu/o = input with internal pull - up (see ? electrical characteristics ? for value) /output.
micrel, inc. ksz9031rnx octobe r 2012 15 m9999 - 10 31 12 - 1.0 strapping options pin number pin name type (1) pin function 35 15 17 phyad2 phyad1 phyad0 i/o i/o i/o the phy a ddress, phyad[2:0], is sampled and latched at power - up/reset and is configur able to any value from 0 to 7. each phy address bit is configured as follows: pull - up = 1 pull - down = 0 phy a ddress bits [4:3] are al ways set to ?00?. 27 28 31 32 mode3 mode2 mode1 mode0 i/o i/o i/o i/o the mode[3:0] strap - in pins are sampled and latched at power - up/reset as follows: mode[3:0] mode 0000 reserved ? not used 0001 reserved ? not used 0010 reserved ? not used 0011 rese rved ? not used 0100 nand t ree m ode 0101 reserved ? not used 0110 reserved ? not used 0111 chip power -d own m ode 1000 reserved ? not used 1001 reserved ? not used 1010 reserved ? not used 1011 reserved ? not used 1100 rgmii mode ? advertise 1000bas e - t full - duplex only 1101 rgmii mode ? advertise 1000base - t full - and half - duplex only 1110 rgmii mode ? advertise all capabilities (10/100/1000 speed half - /full - duplex), except 1000base - t half - duplex 1111 rgmii mode ? advertise all capabilities (10/100 /1000 speed half - /full - duplex) 33 clk125_en i/o clk125_en is sampled and latched at power - up/reset and is defined as follows: pull - up = enable 125mhz clock o utput pull - down = disable 125mhz clock o utput pin 41 (clk125_ndo) provides the 125 mhz referenc e clock output option for use by the mac. 41 led_mode i/o led_mode is latched at power - up/reset and is defined as follows: pull - up = single - led m ode pull - down = tri - color dual - led m ode note: 1. i/o = bi - directional. pin strap - ins are latched during power - up or reset. in some systems, the mac receive input pins may be driven during power - up or reset, and consequently cause the phy strap - in pins on the r gmii signals to be latched to an incorrect con figuration. in this case, micrel recommend s add ing external pull - ups/ pull - downs on the phy strap - in pins to ensure the phy is configured to the correct pin strap - in mode.
micrel, inc. ksz9031rnx octobe r 2012 16 m9999 - 10 31 12 - 1.0 functional overview the ksz9031r nx is a completely integrated triple - speed (10base - t/100base - tx/1000base - t) ethernet p hysical layer t ransceive r solution for transmission and reception of data over a standard cat - 5 unshielded twisted pair (utp) cable. its on- chip proprietary 1000base - t transceiver and manchester/mlt - 3 signaling - based 10base - t/100base - tx transceivers are all ieee 802.3 compliant. the ksz9031r nx reduces board cost and simplifies board layout by using on - chip termination resistors for the four differential pairs and by integrating a n ldo controller to drive a low - cost mosfet to supply the 1.2v core. on the copp er media interface, the ksz9031r nx can automatically detect and correct for differential pair misplacements and polarity reversals, and correct propagation delays and re - sync timing between the four differential pairs, as specified in the ieee 802.3 standard for 1000base - t opera tion. the ksz9031r nx provides the r gmii interface for direct and seamless connection to rgmii macs in gigabit ethernet processors and s witches for data transfer at 10/100/1000 mbps . figure 1 shows a high - level block diagram of the ksz9031 r nx. figure 1 . ksz9031r nx block diagram
micrel, inc. ksz9031rnx octobe r 2012 17 m9999 - 10 31 12 - 1.0 functional description: 10base- t/100base - tx transceiver 100base - tx transmit the 100base - tx tran smit function performs parallel - to - serial conversion, 4b/5b coding , scrambling, nrz - to - nrzi conversion, and mlt - 3 encoding and transmission. the circuitry starts with a parallel - to - serial conversion, which converts the rg mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further con verted from nrz - to - nrzi format then transmitted in mlt - 3 current output. the output current is set by an external 12.1 k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp - pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated in to the 100base - tx transmitter. 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt - 3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - paral lel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. because the amplitude loss and phase distortion are a function of the cable length, the equalizer must ad just its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an o ngoing process and self - adjusts against environmental changes such as temperature variations. next, the equalized signal goes th rough a dc - restoration and data - conversion block. the dc - restoration circuit compensate s for the effect of baseline wander and i mprove s the dynam ic range. the differential data - conversion circuit converts the mlt - 3 format back to nrzi. the slicing threshold is also adaptive. the clock - recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de - scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the r gmii format and provided as the input data to the mac. scrambler/de - scrambler (100base - tx only) the purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled using an 11 - bit wide linear feedback shift register (lfsr ). the scrambler generates a 2047 - bit non - repetitive sequence, then the receiver de - scrambles the incoming data stream using the same sequence as at the transmitter. 10base - t transmit the 10base - t output drivers are incorporated into the 100base - tx drivers to allow for transmission with the same magnetic. the driv ers perform internal wave - shaping and pre - emphasis, and output signals with a typical amplitude of 2.5v peak for standard 10base - t mode and 1.75v peak for energy - efficient 10base - te mode. the 10bas e - t/10base - te signals have harmonic contents that are at least 31db below the fundamental frequency when driven by an all - ones manchester - encoded signal. 10base - t receive on the recei ve side, input buffer and level - detecting squelch circuits are used . a di fferential input receiver circuit and a phase - locked loop (pll) perform the decoding function. the manchester - encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 300mv or with short pulse widths to prevent noises at the receive inputs from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz9031 r nx decodes a data frame. the receiver clock is maintained active during id le periods between receiving data frames. auto - polarity correction is provided for the receive differential pair to automatically swap and fix the incorrect +/ ? polarity wiring in the cabling.
micrel, inc. ksz9031rnx octobe r 2012 18 m9999 - 10 31 12 - 1.0 functional description: 1000base - t transceiver the 1000base - t transceiver is based - on a mixed - signal/digital - signal processing (dsp) architecture, which includes the analog front - end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross - talk cancellers, precision clock recovery scheme, and po wer - efficient line drivers. figure 2 shows a high - level block diagram of a single channel of the 1000base - t transceiver for one of the four differential pairs. figure 2 . ksz9031r nx 100 0base - t transceiver block diagram ? single channel analog echo - cancellation circuit in 1 000base - t mode, the analog echo - cancellation circuit helps to reduce the near - end echo. this analog hybrid circuit relieves the burden of the adc and the adaptive equa lizer. this circuit is disabled in 10base - t/100base - tx mode. automatic gain control (agc) in 1000base - t mode, the automatic gain control (agc) circuit provides initial gain adjustment to boost up the signal level. this pre - conditioning circuit is used to i mprove the signal - to - noise ratio of the receive signal.
micrel, inc. ksz9031rnx octobe r 2012 19 m9999 - 10 31 12 - 1.0 analog - to - digital converter (adc) in 1000base - t mode, the analog - to - digital converter (adc) digitizes the incoming signal. adc performance is essential to the overall performance of the transceiver. t his circuit is disabled in 10base - t/100base - tx mode. timing recovery circuit in 1000base - t mode, the mixed - signal clock recovery circuit together with the digital phase - locked loop is used to recover and track the incoming timing information from the rece ived data. the digital phase - locked loop has very low long - term jitter to maximize the signal - to - noise ratio of the receive signal. the 1000base - t slave phy must transmit the exact receive clock frequency recovered from the received data back to the 1000ba se - t master phy. otherwise, the master and slave will not be synchronized after long transm ission. t his also helps to facilitate echo cancellation and next removal. adaptive equalizer in 1000base - t mode, the adaptive equalizer provides the following functi ons: ? detection for partial response signaling ? removal of next and echo noise ? channel equalization signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch. the ksz9031 r nx uses a digital echo cancel ler to further reduce echo components on the receive signal. in 1000base - t mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels). this results in high - frequency cross - talk coming from adjacent wires. the ks z9031 r nx uses three next cancellers on each receive channel to minimize the cross - talk induced by the other three channels. in 10base - t/100base - tx mode, the adaptive equalizer needs only to remove the inter - symbol interference and recover the channel loss from the incoming data. trellis encoder and decoder in 1000base - t mode, the transmitted 8 - bit data is scrambled into 9 - bit symbols and further encoded into 4d - pam5 symbols. the initial scrambler seed is determined by the specific phy address to reduce emi when more than one ksz9031r nx is used on the same board. on the receiving side, the idle stream is examined first. the scrambler seed, pair skew, pair order , and polarity must be resolved through the logic. the incoming 4d - pam5 data is then converted into 9 - bit symbols and de - scrambled into 8 - bit data. functional description : 10/100/1000 transceiver features auto mdi/mdi - x the automatic mdi/mdi - x feature eliminates the need to determine whether to use a straight cable or a crossover cable between the ksz90 31 r nx and its link partner. this auto - sense function detects the mdi/mdi - x pai r mapping from the link partner, and assigns the mdi/md i - x pair mapping of the ksz9031r nx accordingly. table 1 shows the ksz9031r nx 10/1 00/1000 pin configuration assignments for mdi/mdi - x pin mapping. pin (rj - 45 pair) mdi mdi -x 1000base -t 100base - tx 10base - t 1000base -t 100base - tx 10base - t txrxp/m_a (1,2) a+/ ? tx +/ ? tx +/ ? b+/ ? rx +/ ? rx +/ ? txrxp/m_b (3,6) b+/ ? rx +/ ? rx +/ ? a+/ ? tx +/ ? tx + / ? txrxp/m_c (4,5) c +/ ? not used not used d +/ ? not used not used txrxp/m_d (7,8) d +/ ? not used not used c +/ ? not used not used table 1 . mdi/mdi - x pin mapping
micrel, inc. ksz9031rnx octobe r 2012 20 m9999 - 10 31 12 - 1.0 auto mdi/mdi - x is enabled by default. it is disabled by writing a one to register 1ch, bit [6]. mdi and mdi - x mode is set by register 1ch, bit [7] if auto mdi/mdi - x is disabled. an isolation transformer with symmetrical transmit and receive data paths is recommended to support a uto mdi/mdi - x. pair - swap, alignment, and polar ity check in 1000base - t mode, the ksz9031r nx ? detects incorrect channel order and automatically restore s the pair order for the a, b, c, d pairs (four channels) ? supports 5010ns difference in propagation delay between pairs of channels in accordance with th e ieee 802.3 standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchronized incorrect pair polarities of the differential signals are automatically corrected for all speeds. wave shaping, slew - rate control , and partial response in communication systems, signal transmission encoding methods are used to provide the noise - shaping feature and to minimize distortion and error in the transmission channel. ? fo r 1000base - t, a special partial - response signaling method is used to provide the band - limiting feature for the transmission path. ? for 100base - tx, a simple sle w - rate control method is used to minimize emi. ? for 10base - t, pre - emphasis is used to extend the signal quality through the cable. pll clock synthesizer the ksz9031r nx generates 125mhz, 25mhz , and 10mhz clocks for system timing. internal clocks are generated from the external 25mhz crystal or reference clock. auto - negotiation the ksz9031 r nx conforms to the a uto - n egotiation protocol, defined in clause 28 of the ieee 802.3 specification. auto - n egotiation allows utp (unshielded t wisted p air) link partners to select the highest common mode of operation. during a uto - n egotiation, link partners advertise capabilities across the utp link to each other, and then compar e their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the operating mode. the following list shows the speed and duplex operation mode from h ighest to lowest. ? priority 1: 1000base - t, full - duplex ? priority 2: 1000base - t, half - duplex ? priority 3: 100base - tx, full - duplex ? priority 4: 100base - tx, half - duplex ? priority 5: 10base - t, full - duplex ? priority 6: 10base - t, half - duplex if auto - n egotiation is not supported or the ksz9031 r nx link partner is forced to bypass auto - n egotiation for 10base - t and 100base - tx modes, the ksz9031 r nx sets its operating mode by observing the input signal at its receiver. this is known as parallel detection, and allows t he ksz9031 r nx to establish a link by listening for a fixed signal protocol in the absence of the auto - n egotiation advertisement protocol. the auto - n egotiation link - up process is shown in figure 3 .
micrel, inc. ksz9031rnx octobe r 2012 21 m9999 - 10 31 12 - 1.0 figure 3 . auto - negotiation flow chart for 1000base - t mode, a uto - n egotiation is always required to estab lish a link. during 1000base - t auto - negotiation, the master and s lave configuration is first re solved between link partners. t hen the link i s established with the highest common capabilities between link partners. auto - n egotiation is enabled by default after power - up or hardware reset. after that , a uto - n egotiation can be enabled or disabled through register 0h, bit [12]. if a uto - n egotiation is disabled, the speed is set by register 0h, bits [6, 13] and the duplex is set by register 0h, bit [8]. if the speed is changed on the fly, the link goes down and auto - n egotiation and parallel detection initiate until a common speed between ksz9031r nx and its link partner is re - established for a link. if the link is already established and there is no change of speed on the fly, the changes ( for example , duplex and pause capabilities) will not take effect unless either a uto - n egotiation is restarted through register 0h, bit [9], or a link - down to link - up transition occurs (that is , disconnecting and reconnecting the cable). after auto - n egotiation is completed, the link status is updated in register 1h, bit [2], and the link partner capabilities are updated i n registers 5h, 6h, 8h, and ah. the auto - n egotiation finite state machines use interval timers to manage the auto - n egotiation process. the duration of these timers under normal operating conditions is summarized in table 2 .
micrel, inc. ksz9031rnx octobe r 2012 22 m9999 - 10 31 12 - 1.0 auto - negotiation interval timers time duration transmit b urst interval 16 ms transmit p ulse interval 68 s flp detect minimum time 17.2 s flp detect maximum time 185 s receive minimum b urst interval 6.8 ms receive maximum b urst interval 112 ms data detect minimum interval 35.4 s data detect maximum interval 95 s nlp test minimum interval 4.5 ms nlp test maximum interval 30 ms link l oss time 52 ms break l ink time 1480 ms parallel d etection wait time 830 ms link e nable wait time 1000 ms table 2 . auto - negotiation timers r gmii interface the reduced gigabi t media independent interface (rg mii ) supports on - chip data - to - clock delay timing according to the rgmii version 2.0 specification, with programming opti ons for external delay timing and to adjust and correct t x and r x timing paths. rgmii provides a common interface between rgmii phys and macs, and has the following key characteristics: ? pin count is reduced from 24 pins for the ieee gigabit media independ ent interface (gmii) to 12 pins for rgmii. ? all speeds (10 mbps, 100mbps, and 1000mbps) are supported at both half - and full - duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each four bits wide, a nibble. in r gmii operation, the r gmii pins function as follow s : ? the mac sources the transmit reference clock, txc, at 125mhz for 1000mbps, 25mhz for 100mbps, and 2.5mhz for 10mbps. ? the phy recovers and sources the receive reference cloc k, rxc, at 125mhz for 1000mbps, 25mhz for 100mbps, and 2.5mhz for 10mbps. . ? for 1000base - t, the transmit data, txd[3:0], is presented on both edges of txc, and the received data, rxd[3:0], is clocked out on both edges of the recovered 125mhz clock, rxc. ? fo r 10base - t/100base - tx, the mac holds tx_ctl low until both phy and mac operate at the same speed. during the speed transition, the receive clock is stretched on either a positive or negative pulse to ensure that no clock glitch is presented to the mac . ? tx_ er and rx_er are combined with tx_en and rx_dv, respectively, to form tx_ctl and rx_ctl. these two rgmii control signals are valid at the falling clock edge. after power - up or reset, the ksz9031rnx is configured to rgmii mode if the mode[3:0] strap - in pin s are set to one of the rgmii mode capability options. see the ? strapping options ? section for available options. the ksz9031rnx has the option to output a 125mhz reference clock on the clk125_ndo pin. this clock provides a lower - cost reference clock alternative for rgmii macs that require a 125mhz crystal or oscillator. the 125mhz clock output is enabled after power - up or reset if the clk125_en strap - in pin is pulled high.
micrel, inc. ksz9031rnx octobe r 2012 23 m9999 - 10 31 12 - 1.0 r gmii signal definition table 3 describes the r gmii signals. refer to the rgmii version 2.0 specification for more detailed information. r gmii signal name (per spec) r gmii signal name (per ksz9031 r nx) pin type (with respect to phy) pin type (with respect to mac) description txc gtx_clk input output transmit reference clock (125mhz for 1000mbps, 25mhz for 100mbps, 2.5mhz for 10mbps) tx_ctl tx_en input output transmit control txd[3:0] txd[3:0] input output transmit data[3:0] rxc rx_clk output input receive refe rence c lock (125mhz for 1000mbps, 25mhz for 100mbps, 2.5mhz for 10mbps) rx_ctl rx_dv output input receive control rxd[3:0] rxd[3:0] output input receive data[3:0] table 3 . r gmii signal definition r gmii signal diagram the ksz90 31r nx r gmii pin connections to the mac are shown in figure 4 . figure 4 . ksz9031r nx r gmii interface rgmii pad skew registers pad skew registers are available for all rgmii pins (clocks, control signals, and data bits) to provide programming op tions to adjust or correct the timing relationship for each rgmii pin. because rgmii is a source - synchronous bus interface, the timing relationship needs to be maintained only within the rgmii pin?s respective timing group. ? rgmii transmit timing group pins: gtx_clk, tx_en, txd[3:0] ? rgmii receive timing group pins: rx_clk, rx_dv, rxd[3:0]
micrel, inc. ksz9031rnx octobe r 2012 24 m9999 - 10 31 12 - 1.0 the following four registers located at mmd address 2h are provided for pad skew programming. address name des cription mode default mmd address 2h, register 4h ? rgmii control signal pad skew 2.4.15:8 reserved reserved rw 0000_0000 2.4.7:4 rx_dv pad skew rgmii rx_ctl output pad skew control (0.06ns/step) rw 0111 2.4.3:0 tx_en pad skew rgmii tx_ctl input pad skew control (0.06ns/step) rw 0111 mmd address 2h, register 5h ? rgmii rx data pad skew 2.5.15:12 rxd3 pad skew rgmii rxd3 output pad skew control (0.06ns/step) rw 0111 2.5.11:8 rxd2 pad skew rgmii rxd2 output pad skew control (0.06ns/step) rw 0111 2 .5.7:4 rxd1 pad skew rgmii rxd1 output pad skew control (0.06ns/step) rw 0111 2.5.3:0 rxd0 pad skew rgmii rxd0 output pad skew control (0.06ns/step) rw 0111 mmd address 2h, register 6h ? rgmii tx data pad skew 2.6.15:12 txd3 pad skew rgmii txd3 outpu t pad skew control (0.06ns/step) rw 0111 2.6.11:8 txd2 pad skew rgmii txd2 output pad skew control (0.06ns/step) rw 0111 2.6.7:4 txd1 pad skew rgmii txd1 output pad skew control (0.06ns/step) rw 0111 2.6.3:0 txd0 pad skew rgmii txd0 output pad skew c ontrol (0.06ns/step) rw 0111 mmd address 2h, register 8h ? rgmii clock pad skew 2.8.15:10 reserved reserved rw 0000_00 2.8.9:5 gtx_clk pad skew rgmii gtx_clk input pad skew control (0.06ns/step) rw 01_111 2.8.4:0 rx_clk pad skew rgmii rx_clk output p ad skew control (0.06ns/step) rw 0_1111 table 4 . rgmii pad skew registers
micrel, inc. ksz9031rnx octobe r 2012 25 m9999 - 10 31 12 - 1.0 the rgmii control signals and data bits have 4 - bit skew settings, while the rgmii clocks have 5 - bit skew settings. each register bit is approximately a 0.06ns step change. a single - bit decrement decreases the delay by approximately 0.06ns, while a sin gle - bit increment increases the delay by approximately 0.06ns. table 5 and table 6 list the approximate absolute delay for each pad skew (value) setting. pad skew (value) delay (ns) 0_0000 ? 0.90 0_0001 ? 0.84 0_0010 ? 0.78 0_0011 ? 0.72 0_0100 ? 0.66 0_0101 ? 0.60 0_0110 ? 0.54 0_0111 ? 0.48 0_1000 ? 0.42 0_1001 ? 0.36 0_101 0 ? 0.30 0_1011 ? 0.24 0_1100 ? 0.18 0_1101 ? 0.12 0_1110 ? 0.06 0_1111 no delay adjustment (default value) 1_0000 +0.06 1_0001 +0.12 1_0010 +0.18 1_0011 +0.24 1_0100 +0.30 1_0101 +0.36 1_0110 +0.42 1_0111 +0.48 1_1000 +0.54 1_1001 +0.60 1_1010 +0.66 1_1011 +0.72 1_1100 +0.78 1_1101 +0.84 1_1110 +0.90 1_1111 +0.96 table 5 . absolute delay for 5 - bit pad skew setting
micrel, inc. ksz9031rnx octobe r 2012 26 m9999 - 10 31 12 - 1.0 pad skew (value) delay (ns) 0000 ? 0.42 0001 ? 0.36 0010 ? 0.30 0011 ? 0.24 0100 ? 0.18 0101 ? 0.12 0110 ? 0.06 0111 no delay adjustment (default value) 1000 +0.06 1001 +0.12 1010 +0.18 1011 +0.24 1100 +0.30 1101 +0.36 1110 +0.42 1111 +0.48 table 6 . absolute delay for 4 - bit pad skew setting when computing the rgmii t iming relationships, delays along the entire data path must be aggregated to determine the total delay to be used for comparison between rgmii pins within their respective timing group. for the transmit data path, total delay includes mac output delay, mac - to - phy pcb routing delay, and phy (ksz9031rnx) input delay and skew setting (if any). for the receive data path, the total delay includes phy (ksz9031rnx) output delay, phy - to - mac pcb routing delay, and mac input delay and skew setting (if any). after pow er - up or reset, the ksz9031rnx defaults to the following timings at its rgmii i/ o pins to support on- chip data - to - clock skew timing according to the rgmii version 2.0 specification: ? transmit inputs: gtx_clk clock is in sync within 500ps of tx_en and txd[ 3:0] ? receive outputs: rx_clk is delayed about 1.2ns with respect to rx_dv and rxd[3:0] the above default rgmii timings imply: ? rx_clk clock skew is set by the ksz9031rnx default register settings. ? gtx_clk clock skew is provided by the mac. ? no pcb delay is r equired for gtx_clk and rx_clk clocks. the following examples show how to read/write to mmd address 2h, register 8h for the rgmii gtx_clk and rx_clk skew settings. mmd register access is through the direct portal registers dh and eh. for more programming d etails, refer to the ? mmd registers ? descriptions ? section. ? read back value of mmd address 2h, register 8h. - w rite register 0x d = 0x0002 // select mmd device address 2h - w rite register 0x e = 0x0008 // select r egister 8h o f mmd device address 2h - w rite register 0x d = 0x4002 // select r egister data for mmd device address 2h, r egister 8h - r ead register 0x e // read value of mmd device address 2h, register 8h
micrel, inc. ksz9031rnx octobe r 2012 27 m9999 - 10 31 12 - 1.0 ? write value 0x03 ff (delay gtx_clk and rx_clk pad skews to their maxi mum values) to mmd address 2h, r egister 8h - w rite register 0xd = 0x0002 // select mmd device address 2h - w rite register 0x e = 0x0008 // select r egister 8h of mmd device address 2h - w rite register 0x d = 0x4002 // select register d ata for mmd device address 2h, r e gister 8h - w rite register 0x e = 0x03 ff // write value 0x03 ff to mmd device address 2h, r egister 8h rgmii in - b and status the ksz9031rnx provides in - band status to the mac during the inter - frame gap when rx_dv is de - asserted. rgmii in - band status is always en abled after power - up. the in - band status is sent to the mac using the rxd[3:0] data pins, and is described in table 7 . rx_dv rxd3 rxd[2:1] rxd0 0 (valid only when rx_dv is low) duplex status 0 = h alf - duplex 1 = f ull - duplex rx_clk clock speed 00 = 2.5mhz (10mbps) 01 = 25mhz (100mbps) 10 = 125mhz (1000mbps) 11 = r eserved link status 0 = link down 1 = link up table 7 . rgmii in - band status mii management (miim) interface the ksz9031r nx sup ports the ieee 802.3 mii management i nterface, also known as the management data input/ output (mdio) i nterface. this interface allows upper - layer devices to monitor and co ntrol the state of the ksz9031r nx. an external device with miim capability is used t o read the phy status and/or configure the phy settings. more detail s about the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates the clock li ne (mdc) and the data line (mdio). ? a specific protocol that operates across the physical connection mentioned earlier, which allows an external controller to communicate with one or more ksz9031 r nx device s . each ksz9031r nx device is assigned a unique phy a ddress between 0h and 7h by the phyad[2:0] strapping pins. ? a 32 - register address s pace for direct access to ieee - defined registers and v endor - specific r egisters, and for indirect access to mmd a ddresses and r egisters. see the ? register map ? section. phy address 0h is supported as the unique phy address only; it is not support ed as the broadcast phy address, which allows for a single write command to simultaneously program an identical phy register for two or more phy dev ices ( for example , using phy address 0h to set register 0h to a value of 0x1940 to set bit [11] to a value of one to enable software power - d own). instead, separate write commands are used to program each phy device. table 8 shows the mii management frame format for the ksz9031 r nx. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta dat a bits [15:0] idle read 32 1?s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 0 1 00aaa rrrrr 10 dddddddd_dddddddd z table 8 . mii management frame format for the ksz9031r nx
micrel, inc. ksz9031rnx octobe r 2012 28 m9999 - 10 31 12 - 1.0 interrupt (int_n) the int_n pin is an optional interrupt signal that is used to inform the external controller that there has been a st atus update in the ksz9031r nx phy register. bits [15:8] of register 1bh are the interrupt control bits that enable and disable the conditions for asserting the int_n signal. bits [7:0] of register 1bh are the interrupt status bits that indicate which inter rupt conditions have occurred. the interrupt status bits are cleared after reading register 1bh. bit [14] of register 1fh sets the interrupt level to active high or active low. the default is active low. the mii m anagement bus option gives the mac processo r complete access to the ksz9031 r nx control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll the phy for status change. led mode the ksz9031r nx provides two programmable led output pins, led2 and led1, whi ch are configurable to support two led modes. the led mode is configured by the led_mode strap - in (pin 41 ) . it is latched at power - up/reset and is defined as follows: ? pull - up: single - led m ode ? pull - down: tri - color dual - led m ode single - led mode in single - led m ode, the led2 pin indicates the link status while the led1 pin indicates the activity status, as shown in table 9 . led p in pin state led definition link/activity led2 h off link off l on link on (any speed) led1 h off no a ctivity toggle blinking activity (rx, tx) table 9 . single - led mode ? pin definition tri - color dual - led mode in tri - color dual - led mode, the link and a ctivity status are indicated by the led2 pin for 1000base - t; by the led1 pin for 100base - tx; and by both led2 and led1 pin s , working in conjunction, for 10base - t. this is summarized in table 10. led pin (state) led pin (definition) link/activity led2 led1 led2 led1 h h off off link off l h on off 1000 link / no a ctivity toggle h blinking off 1000 link / activity (rx, tx) h l off on 100 link / no a ctivity h toggle off blinking 100 link / activity (rx, tx) l l on on 10 link / no a ctivity toggle toggle blinking blinki ng 10 link / activity (rx, tx) table 10 . tri - color dual - led mode ? pin definition each led output pin can directly drive a n led with a series resistor (typically 220 ? to 470 ? ).
micrel, inc. ksz9031rnx octobe r 2012 29 m9999 - 10 31 12 - 1.0 loopback mode the ksz9031r nx supports the following loopback operations to verify analog and/or digital data paths. ? local (d igital) l oopback ? remote (a nalog) l oopback local (digital) loopback this loopback mode checks the r gmii transmit and receive data paths between ksz9031 r nx and external mac, and is s upp orted for all three speeds (10/100/1000mbps) at full - duplex. the loopback data path is shown in figure 5 . 1. r gmii mac transmits frames to ksz9031 r nx. 2. frames are wrapped around inside ksz9031 r nx. 3. ksz9031r n x transmits frames back to r gmii mac. figure 5 . local (digital) loopback the following programming steps and register settings are used for local l oopback mode. for 1000 mbps loopback, 1. set r egister 0h, ? bit [14] = 1 // enable local l oo pback mode ? bits [6, 13] = 10 // select 1000mbps speed ? bit [12] = 0 // disable a uto - n egotiation ? bit [8] = 1 // select full - duplex mode 2. set r egister 9h, ? bit [12] = 1 // enabl e m aster - s lave manual configuration ? bit [11] = 0 // select s lave configur ation ( required for loopback mode) for 10/100 mbps loopback, 1. set r egister 0h, ? bit [14] = 1 // enable l ocal l oopback mode ? bits [6, 13] = 00 / 01 // select 10mbps/100mbps speed ? bit [12] = 0 // disable auto - n egotiation ? bit [8] = 1 // select full - dupl ex mode
micrel, inc. ksz9031rnx octobe r 2012 30 m9999 - 10 31 12 - 1.0 remote (analog) loopback this loopback mode checks the line (differential pairs, transformer, rj - 45 connector, ethernet cable) transmit and receive data paths between ksz9031 r nx and its link partner, and is s upported for 1000base - t full - duplex mode only. the loopback data path is shown in figure 6 . 1. the gigabit phy l ink p artner transmits frames to ksz9031 r nx. 2. frames are wrapped around inside ksz9031 r nx. 3. ksz9031 r nx transm its frames back to the gigabit phy l ink p artner. figure 6 . remote (analog) loopback the following programming steps and register settings are used for remote l oopback mode. 1. set r egister 0h, ? bits [6, 13] = 10 // select 1000mbps speed ? bit [12] = 0 // disable auto - n egotiation ? bit [8] = 1 // select full - duplex mode or just auto - negotiate and li nk up at 1000base - t full - duplex mode with link partner . 2. set register 11h, ? bit [8] = 1 // enable remote l oopback mode
micrel, inc. ksz9031rnx octobe r 2012 31 m9999 - 10 31 12 - 1.0 linkmd ? cable diagnostic the linkmd function use s time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems, such as open circuits, short circuits , and impedance mismatches. linkmd operates by sending a pulse of known amplitude and duration down the selected differential p air, then analyzing the polarity and shape of the reflected signal to determine the type of fault: open circuit for a positive/non - inverted amplitude reflection and short circuit for a negative/inverted amplitude reflection. the time duration for the refle cted signal to return provides the approximate distance to the cabling fault . the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 12h, the linkmd ? cable diagnostic r egister, in conjunction with register 1ch, the auto mdi/mdi - x r egister. the latter reg ister is needed to disable the a uto mdi/mdi - x function before running the linkmd test. additionally, a software reset (reg. 0h, bit [15] = 1) should be performed before and after running the linkmd test. the reset helps to ensure the ksz9031 r nx is in the normal operating state before and after the test. nand tree support the ksz9031r nx provides parametric nand tree support for fault detecti on between chip i/os and board. nand tree mode is enabled at power - up/reset with the mode[3:0] strap - in pins set to ?0100? . table 11 lists the nand tree pin order. pin description led2 input led1 /pme_n1 input txd0 input txd1 input txd2 input txd3 input gtx_clk input tx_en input rx_dv input rx_clk input int_n /pme_n2 input mdc input mdio input clk125_ndo output table 11 . nand tree test pin order for ksz9031 r nx
micrel, inc. ksz9031rnx octobe r 2012 32 m9999 - 10 31 12 - 1.0 power manage ment the ksz9031r nx incorporates a numbe r of power - management modes and features that provide methods to consume less energy. these are discussed in the following sections. energy - detect power - down mode energy - detect power - d own (edpd) m ode is used to furth er reduce the transceiver power consumption when the cable is unplugged. it is enabled by writing a one to mmd address 1ch, register 23h, bit [0], and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). in edpd mode, the ksz9031 r nx shuts down all transceiver blocks, except for the transmitter and energy detect circuits. p ower can be reduced further by extending the time interval between the transmissions of link pulses to check for the presence of a link partner. the periodic transmission of link pulses is needed to ensure the ksz9031rnx and its link partner, when operating in the same low - power state and w ith auto mdi/mdi - x disabled , can wake up when the cable is connected between them. by default, edpd m ode is disabl ed after power - up. software power - down mode this mode is used to power down the ksz9031r nx device when it is not in use after power - up. software p ower - down (spd) m ode is enabled by writing a one to register 0h, bit [11] . in the spd state, the ksz9031r nx di sables all internal functions, except for the mii m anagement interface. the ksz9031 r nx exits the spd state after a zero is written to register 0h, bit [11]. chip power - down mode this mode provides the low est power state for the ksz9031r nx device when it is mounted on the board but not in use . chip power - down (cpd) m ode is enabled after power - up/reset with the mode[3:0] strap - in pins set to ?0111? . the ksz9031rnx exits cpd m ode after a hardware reset is applied to the reset_n pin (pin 42 ) with the mode[3:0] strap - in pins set to an operating mode other than cpd. energy efficient ethernet (eee) the ksz9031rnx implements e nergy e fficient ethernet (eee) as described in ieee standard 802.3az for line signaling by the four differential pairs (analog side) and acco rding to the multisource agreement (msa) of collaborating gigabit ethernet chip vendors for the rgmii (digital side). this agreement is based on the ieee standard?s eee implementation for gmii (1000mbps) and mii (100mbps). the specification is defined arou nd an e ee - compliant mac on the host side and an eee - compliant link partner on the line side that support the special signaling associated with eee. eee saves power by keeping the ac signal on the copper ethernet cable at approximately 0v peak - to - peak as of ten as possible during periods of no traffic activity, while maintaining the link - up status. this is referred to as low - power idle (lpi) mode or state. during lpi mode, the copper link respond s automatically when it receives traffic and resume s normal phy operation i m mediately, without blockage of traffic or loss of packet . this involves e xiting lpi mode and returning to normal 100/1000mbps operating mode. wake - up times are <16 s for 1000base - t and <30 s for 100base - tx. the lpi state is controlled independ ently for transmit and receive paths, allowing the lpi state to be active (enabled) for: ? transmit cable path only ? receive cable path only ? both transmit and receive cable paths th e ksz9031r nx has the eee function disabled as the power - up default setting. t he eee function is enable d by setting the following eee a dvertisement bits at mmd address 7h, register 3ch, followed by restarting a u to - n egotiation (writing a ?1? to register 0h, bit [9]): ? bit [2] = 1 // enable 1000mbps eee mode ? bit [1] = 1 // enable 100m bps eee mode for sta ndard (non - eee) 10base - t mode, normal link p ulses (nlps) with long periods of no ac signal transmission are used to maintain the link during the idle period when there is no traffic activity. to save more power , the ksz9031r nx provides the option to enable 10base - te mode , which saves additional power by reducing the transmitted signal amplitude from 2.5v to 1.75v. to enable 10base - te mode, write a ?1? to mmd address 1ch, register 4h, bit [10].
micrel, inc. ksz9031rnx octobe r 2012 33 m9999 - 10 31 12 - 1.0 durin g lpi mode, r efresh transmissions are used to maintain the link ; power savings occur in q uiet periods . approximately every 20 to 22 milliseconds , a refresh transmission of 200 to 220 microseconds is sent to the link partner. the r efresh transmissions and q uiet periods are shown in figure 7 . figure 7 . lpi mode (refresh t ransmissions and quiet p eriods) transmit direction control (mac - to - phy) rgmii 1000mbps transmission from mac - to - phy u ses both rising and falling edges of th e gtx_clk clock. the ksz9031rnx uses the tx_en pin as the rgmii transmit control signal (tx_ctl) to clock in the tx_en signal on the rising edge and the tx_er signal on the falling edge . it also uses the txd[3:0] pins to clock in the tx data low nibble bit s [3:0] on the rising edge and the tx data high nibble bits [7:4] on the falling edge. the ksz9031rnx enters lpi mode for the transmit direction when its attached eee - compliant mac de - asserts the tx_en signal (the tx_ctl pin outputs low on the rising edge) , asserts the tx_er signal (the tx_ctl pin outputs high on the falling edge), and sets tx data bits [7:0] to 0000_0001 (txd[3:0] pins output 0001 on the rising edge and 0000 on the falling edge). the ksz9031rnx rem ains in the 1000mbps transmit lpi state wh ile the mac maintains the states of these signals. when the mac changes any of the tx_en, tx_er, or tx data signals from their lpi state values, the ksz9031rnx exits the lpi transmit state. to save more power, the mac can stop the gtx_clk clock after the r gmii signals for the lpi state have been asserted for 10 or more gtx_clk clock cycles . figure 8 shows the lpi transition for rgmii transmit in 1000mbps mode . figure 8 . lpi transition ? rgmii (1000mbps) transmit
micrel, inc. ksz9031rnx octobe r 2012 34 m9999 - 10 31 12 - 1.0 rgmii 100mbps transmission from mac - to - phy uses both rising and falling edges of the gtx_clk clock. the ksz9031rnx uses the tx_en pin as the rgmii transmit control signal (tx_ctl) to clock in the tx_en signal on the rising edge and the tx_er signal on the falling edge. it also uses the txd[3:0] pins to clock in the tx data bits [3:0] on the rising edge. the ksz9031rnx enters lpi mode for the transmit direction when its attached eee - compliant mac de - asserts the tx_en signal (the t x_ctl pin outputs low on the rising edge), asserts the tx_er signal (the tx_ctl pin outputs high on the falling edge), and sets tx data bits [3:0] to 0001 (the txd[3:0] pins output 0001 ). the ksz9031rnx rem ains in the 100mbps transmit lpi state while the m ac maintains the states of these signals. when the mac changes any of the tx_en, tx_er, or tx data signals from their lpi state values, the ksz9031rnx exits the lpi transmit state. to save more power, the mac can stop the gtx_clk clock after the rgmii sign als for the lpi state have been asserted for 10 or more gtx_clk clock cycles. figure 9 shows the lpi transition for rgmii transmit in 100mbps mode . figure 9 . lpi transition ? rgmii (1 0 0mbps) transmit receive direction control (phy - to - mac) rgmii 1000mbps transmission from phy - to - mac uses both rising and falling edges of the rx_clk clock . the ksz9031rnx uses the rx_dv pin as the rgmii receive control signal (rx_ctl) to clock out the rx_d v signal on the rising edge and the rx_er signal on the falling edge it also uses the rxd[3:0] pins to clock out the rx data low nibble bits [3:0] on the rising edge and the rx data high nibble bits [7:4] on the falling edge. the ksz9031rnx enters lpi mode for the receive direction when it receives the /p/ code bit pattern (sleep/r efresh) from its e ee- compliant link partner. it then drives the rx_dv pin low on the rising clock edge and high on the falling clock edge to de - assert the rx_dv signal and assert the rx_er signal, respectively, to the mac. also, the rxd[3:0] pins are driven to 0001 on the rising clock edge and 0000 on the falling clock edge to set the rx data bits [7:0] to 0000_0001 . the ksz9031rnx rem ains in the 1000mbps receive lpi state while it continues to receive the refresh from its link partner, so it will continue to maintain and drive the lpi output states for th e rgmii receive output pins to inform the attached eee - compliant mac that it is in the receive lpi state. when the ksz9031rnx rec eives a non /p/ code bit pattern (non refresh), it exits the receive lpi state and sets the rx_dv and rxd[3:0] output pins accordingly for a normal frame or normal idle. t o save more power , t he ksz9031rnx stops the rx_clk clock output to the mac after 10 o r more rx_clk clock cycles have occurred in the receive lpi state . figure 10 shows the lpi transition for rgmii receive in 1000mbps mode .
micrel, inc. ksz9031rnx octobe r 2012 35 m9999 - 10 31 12 - 1.0 figure 10 . lpi transition ? rgmii (1000mbps) r eceive rgmii 100mbps transmission from phy - to - mac uses both rising and falling edges of the rx_clk clock. the ksz9031rnx uses the rx_dv pin as the rgmii receive control signal (rx_ctl) to clock out the rx_dv signal on the rising edge and the rx_er signal on the falling edge. it also uses the rxd[3:0] pins to clock out the rx data bits [3:0] on the rising edge. the ksz9031rnx enters lpi mode for the receive direction when it receives the /p/ code bit pattern (sleep/refresh) from its e ee- compliant link partn er. it then drives the rx_dv pin low on the rising clock edge and high on the falling clock edge to de - assert the rx_dv signal and assert the rx_er signal, respectively, to the mac. also, t he rxd[3:0] pins are driven to 0001 . the ksz9031rnx rem ains in the 100mbps receive lpi state while it continues to receive the refresh from its link partner, so it will continue to maintain and drive the lpi output states for th e rgmii receive output pins to inform the attached eee - compliant mac that it is in the receive lpi state. when the ksz9031rnx receives a non /p/ code bit pattern (non - refresh), it exits the receive lpi state and sets the rx_dv and rxd[3:0] output pins accordingly for a normal frame or normal idle. the ksz9031rnx stops the rx_clk clock output to the mac after 10 or more rx_clk clock cycles have occurred in the receive lpi state to save more power. figure 11 shows the lpi transition for rgmii receive in 100mbps mode . figure 11 . lpi transition ? rg mii (100mbps) receive
micrel, inc. ksz9031rnx octobe r 2012 36 m9999 - 10 31 12 - 1.0 registers associated with eee the following mmd registers are provided for eee configuration and management: ? mmd address 3h, reg ister 0h - pcs eee ? control r egister ? mmd address 3h, registe r 1h - pcs eee ? status r egister ? mmd address 7h, register 3ch - eee advertisement r egister ? mmd addres s 7h, register 3dh - eee link partner advertisement r egister wake -o n- lan wake - o n - lan (wol) is normally a mac - based function to wake up a host system (for example, an ethernet end device, such as a pc) that is in standby power mode. wake - up is triggered by receiving and detecting a special packet (commonly referred to as the ? magic p acket?) that is sent by the r emote link partner. the ksz9031r nx can perform the same wol functio n if the mac address of its associated mac device is entered into the ks z9031 r nx phy registers for m agic - p acket detection. when the ksz9031rnx detects the m agic p acket, it wakes up the host by driving its power m anagement e vent (pme) output pin low. by def ault, the wol function is disabled. it is enabled by setting the enabling bit and configuring the associated registers for the selected pme wake - up detection method. the ksz9031 r nx provides three methods to trigger a pme wake - up: ? magic - p acket d etection ? cus tomized - packet d etection ? link s tatus change d etection magic - packet detection the magic p ack et?s frame format starts with 6 bytes of 0xffh and is followed by 16 repetitions of the mac address of its associated mac device (local mac device). when the m agic p acket is detec t ed from its link partner, the ksz9031 r nx asserts its pme output pin low. the following mmd address 2h registers are provided for magic - p acket detection: ? magic - p acket detection is enabled by writing a ?1? to mmd address 2h, register 10h, bit [6] ? the mac address (for the local mac device) is written to and stored in mmd address 2h, registers 11h ? 13h the ks z9031r nx does not generate the m agic p acket. the m agic p acket must be provided by the external system. customized - packet detection the c ust omized p acket has associated register/bit masks to select which byte , or bytes , of the first 64 bytes of the packet to use in the crc calculation. after the ksz9031r nx receives the packet from its link partner, the selected bytes for t he received packet ar e used to calculate the crc. the calculated crc is compared to the expected crc value that was previously written to and stored in the ksz9031 r nx phy registers. if there is a match, the ksz9031 r nx asserts its pme output pin low. four c ustomized p ackets are provided to support four types of wake - up scenarios. a dedicated set of registers is use d to configure and enable each c ustomized p acket. the following mmd registers are provided for customized - p acket detection: ? each of the four c ustomize d p ackets is enab led via mmd address 2h, register 10h, - bit [2] // f or customized p ackets, type 0 - bit [3] // f or customized p ackets, type 1 - bit [4] // f or customized p ackets, type 2 - bit [5] // f or customized p ackets, type 3
micrel, inc. ksz9031rnx octobe r 2012 37 m9999 - 10 31 12 - 1.0 ? 32- bit expected crcs are written to and stored i n: - mmd address 2h, registers 14h ? 15h // f or customized p ackets, type 0 - mmd address 2h, registers 16h ? 17h // f or customized p ackets, type 1 - mmd address 2h, registers 18h ? 19h // f or customized p ackets, type 2 - mmd address 2h, registers 1ah ? 1bh // f or customized p ackets, type 3 ? masks to indicate which of the first 64 - bytes to use in the crc calculation are set in: - mmd address 2h, regi sters 1ch ? 1fh // fo r customized p ackets, type 0 - mmd address 2h, registers 20h ? 23h // f or c ustomi zed p ackets, type 1 - m md address 2h, registers 24h ? 27h // f or customized p ackets, type 2 - mmd address 2h, registers 28h ? 2bh // f or customized p ackets, type 3 ? 32- bit calculated crcs (of receive packet) are stored in: - mmd address 2h, registers 30h ? 31h // f or customized p acke ts, type 0 - mmd address 2h, registers 32h ? 33h // f or customized p ackets, type 1 - mmd address 2h, registers 34h ? 35h // f or customized p ackets, type 2 - mmd address 2h, registers 36h ? 37h // f or customized p ackets, type 3 link status change detection if lin k s tatus change d etection is enabled, the ksz9031 r nx asserts its pme output pin low whenever there is a link status change , using the following mmd address 2h register bits and their enabled (1) or disabled (0) settings: ? mmd addres s 2h, register 10h, bit [0] // f or link - up detection ? mmd addres s 2h, register 10h, bit [1] // f or link - down detection the pme output signal is availab le on either led1/pme_n1 (pin 17 ) or int_n/pme _n2 (pin 38 ), and is selected and enabled using mmd address 2h, register 2h, bits [8 ] and [10], respectively. additionally, mmd address 2h, register 10h, bits [15:14] defines the output function s for pins 1 7 and 38. the pme output is active low and requires a 1 k pull - up to the vddio supply. when asserted, the pme output is cleared by disabling the register bit that e nabled the pme trigger source (magic packet, c ustomized packet, l ink s tatus change ).
micrel, inc. ksz9031rnx octobe r 2012 38 m9999 - 10 31 12 - 1.0 typical current/power consumption table 12 through table 15 show the typical current consumption by the core (dvddl, avddl, avddl_pll), tran sceiver (avddh) and digital i/o (dvddh) supply pins, and the total typical power for the enti re ksz9031 r nx device for va rious nominal operating voltage combinations. transceiver (3.3v), digital i/os (3.3v) condition 1.2v core (dvddl, avddl, avddl_pll) 3.3v transceiver (avddh) 3.3v digital i/os (dvddh) total chip power ma ma ma mw 1000base - t li nk - up (no traffic) 210 67.4 19.5 538 1000base - t full - duplex @ 100% utilization 221 66.3 41.5 621 100base - tx link - up (no traffic) 63.6 28.7 13.9 217 100base - tx full - duplex @ 100% utilization 63.8 28.6 17.2 228 10base - t link - up (no traffic) 7.1 15.9 11.5 99 10base - t full - duplex @ 100% utilization 7.7 28.6 13.7 149 eee mode ? 1000mbps 43.5 5.7 30.6 172 eee mode ? 100mbps (tx and rx in lpi) 25.6 5.3 18.1 108 software power - down mode (reg. 0h.11 = 1) 1.0 4.2 9.3 46 table 12 . ty pical current/ power consumption ? transceiver (3.3v), digital i/os (3.3v) transceiver (3.3v), digital i/os (1.8v) condition 1.2v core (dvddl, avddl, avddl_pll) 3.3v transceiver (avddh) 1.8v digital i/os (dvddh) total chip power ma ma ma mw 1000base -t link - up (no traffic) 210 67.4 11.2 494 1000base - t full - duplex @ 100% utilization 221 66.3 23.6 526 100base - tx link - up (no traffic) 63.6 28.7 8.4 186 100base - tx full - duplex @ 100% utilization 63.8 28.6 9.8 189 10base - t link - up (no traffic) 7.1 15.9 3.6 67 10base - t full - duplex @ 100% utilization 7.7 28.6 5.6 114 eee mode ? 1000mbps 43.5 5.7 15.9 100 eee mode ? 100mbps (tx and rx in lpi) 25.6 5.3 9.1 65 software power - down mode (reg. 0h.11 = 1) 1.0 4.2 5.5 25 table 13 . typica l current / power consumption ? transceiver (3.3v), digital i/os (1.8v)
micrel, inc. ksz9031rnx octobe r 2012 39 m9999 - 10 31 12 - 1.0 transceiver (2.5v), digital i/os (2.5v) condition 1.2v core (dvddl, avddl, avddl_pll) 2.5v transceiver (1) (avddh ? commercial temp only) 2.5v digital i/os (dvddh) total chip power m a ma ma mw 1000base - t link - up (no traffic) 210 58.8 14.7 435 1000base - t full - duplex @ 100% utilization 221 57.9 31.5 488 100base - tx link - up (no traffic) 63.6 24.9 10.5 165 100base - tx full - duplex @ 100% utilization 63.8 24.9 13.0 171 10base - t link -up ( no traffic) 7.1 11.5 6.3 53 10base -t f ull - duplex @ 100% utilization 7.7 25.3 9.0 95 eee mode ? 1000mbps 43.5 4.5 23.6 122 eee mode ? 100mbps (tx and rx in lpi) 25.6 4.1 13.8 75 software power - down mode (reg. 0h.11 = 1) 1.0 3.1 6.7 26 table 14 . typical current/power consumption ? transceiver (2.5v), digital i/os (2.5v) transceiver (2.5v), digital i/os (1.8v) condition 1.2v core (dvddl, avddl, avddl_pll) 2.5v transceiver (1 ) (avddh ? commercial temp only) 1.8v digital i/os (dvd dh) total chip power ma ma ma mw 1000base - t link - up (no traffic) 210 58.8 11.2 419 1000base - t full - duplex @ 100% utilization 221 57.9 23.6 452 100base - tx link - up (no traffic) 63.6 24.9 8.4 154 100base - tx full - duplex @ 100% utilization 63.8 24.9 9.8 1 56 10base -t l ink - up (no traffic) 7.1 11.5 3.6 44 10base -t f ull - duplex @ 100% utilization 7.7 25.3 5.6 83 eee mode ? 1000mbps 43.5 4.5 15.9 92 eee mode ? 100mbps (tx and rx in lpi) 25.6 4.1 9.1 57 software power - down mode (reg. 0h.11 = 1) 1.0 3.1 5.5 1 9 table 15 . typical current/power consumption ? trans ceiver (2.5v), digital i/os (1.8 v) note: 1. 2.5v avddh is recommended for commercial temperature range (0c to +70c) operation only.
micrel, inc. ksz9031rnx octobe r 2012 40 m9999 - 10 31 12 - 1.0 register map the register space within t he ksz90 31r nx consists of two distinct areas. ? standard r egisters // d irect register access ? mdio manageable device (mmd) r egisters // i ndirect register access the ksz9031r nx supports the following s tandard r egisters. register number (hex) description ie ee- defined registers 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto - negotiation advertisement 5h auto - negotiation link partner ability 6h auto - negotiation expansion 7h auto - negotiation next page 8h auto - negotiatio n link partner next page ability 9h 1000base - t control ah 1000base - t status bh ? ch reserved dh mmd access ? control eh mmd access ? register/data fh extended status vendor - specific registers 10h reserved 11h remote loopback 12h linkmd cable diag nostic 13h digital pma/pcs status 14h reserved 15h rxer counter 16h ? 1ah reserved 1bh interrupt control/status 1ch auto mdi/mdi - x 1dh ? 1eh reserved 1fh phy control table 16 . standard registers supported by ksz9031r nx the ksz9031r nx supports the following mmd d evice a ddresses and their associated r egister a ddresses, w hich make up the indirect mmd r egisters.
micrel, inc. ksz9031rnx octobe r 2012 41 m9999 - 10 31 12 - 1.0 device address (hex) register address (hex) description 1h 5ah 1000base - t link - u p time control 2h 0h common co ntrol 1h strap status 2h operation mode strap override 3h operation mode strap status 4h r gmii control signal pad skew 5h rgmii rx data pad skew 6h rgmii tx data pad skew 8h r gmii clock pad skew 10h wake - on - lan ? control 11h wake - on - lan ? magic packet, mac - da - 0 12h wake - on - lan ? magic packet, mac - da - 1 13h wake - on - lan ? magic packet, mac - da - 2 14h wake - on - lan ? customized packet, type 0, expected crc 0 15h wake - on - lan ? customized packet, type 0, expected crc 1 16h wake - on - lan ? cu stomized packet, type 1, expected crc 0 17h wake - on - lan ? customized packet, type 1, expected crc 1 18h wake - on - lan ? customized packet, type 2, expected crc 0 19h wake - on - lan ? customized packet, type 2, expected crc 1 1ah wake - on - lan ? customized packet, type 3, expected crc 0 1bh wake - on - lan ? customized packet, type 3, expected crc 1 1ch wake - on - lan ? customized packet, type 0, mask 0 1dh wake - on - lan ? customized packet, type 0, mask 1 1eh wake - on - lan ? customized packet, type 0, mask 2 1fh wake - on - lan ? customized packet, type 0, mask 3 20h wake - on - lan ? customized packet, type 1, mask 0 21h wake - on - lan ? customized packet, type 1, mask 1 22h wake - on - lan ? customized packet, type 1, mask 2 23h wake - on - lan ? customized packet, t ype 1, mask 3 24h wake - on - lan ? customized packet, type 2, mask 0 25h wake - on - lan ? customized packet, type 2, mask 1 26h wake - on - lan ? customized packet, type 2, mask 2 27h wake - on - lan ? customized packet, type 2, mask 3 28h wake - on - lan ? custom ized packet, type 3, mask 0 29h wake - o n - lan ? customized packet, type 3, mask 1 2ah wake - o n - lan ? customized packet, type 3, mask 2 2bh wake - o n - lan ? customized packet, type 3, mask 3 3h 0h pcs eee ? control 1h pcs eee ? status 7h 3ch eee adverti sement 3dh eee link partner advertisement 1ch 4h analog control 4 23h edpd control table 17 . mmd registers s upported by ksz9031 r nx
micrel, inc. ksz9031rnx octobe r 2012 42 m9999 - 10 31 12 - 1.0 standard registers standard r egisters provide direct read/write access to a 32 - register addre ss space, as defined in clause 22 of the ieee 802.3 specification. within this address space, the first 16 registers (registers 0h to fh) are defined according to the ieee specification, while the remaining 16 registers (registers 10h to 1fh) are defined s pecific to the phy vendor. ieee defined registers ? descriptions address name description mode (1) default register 0h ? basic control 0.15 reset 1 = software phy reset 0 = normal operation this bit is self - cleared after a ?1? is written to it. rw/sc 0 0.14 loop back 1 = loop back mode 0 = normal operation rw 0 0.13 speed select (lsb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000 mbps [0,1] = 100 mbps [0,0] = 10 mbps this bit is ignored if auto -n egotiation is enabled (reg. 0.12 = 1). rw 0 0.12 auto - negotiat ion enable 1 = enable a uto -n egotiation process 0 = disable a uto -n egotiation process if enabled, a uto -n egotiation result overrides settings in reg. 0.13, 0.8 and 0.6. rw 1 0.11 power - down 1 = power - down mode 0 = normal operation rw 0 0.10 isolate 1 = elec trical isolation of phy from r gmii 0 = normal operation rw 0 0.9 restart auto - negotiation 1 = restart auto - n egotiation process 0 = normal operation this bit is self - cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full - duplex 0 = half - du plex rw 1 0.7 reserved reserved rw 0 0.6 speed select (msb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000mbps [0,1] = 100mbps [0,0] = 10mbps this bit is ignored if auto - negotiation is enabled (reg. 0.12 = 1). rw set by mode[3:0] strapping pins. see the ? strapping options ? section for details. 0.5:0 reserved reserved ro 00_0000
micrel, inc. ksz9031rnx octobe r 2012 43 m9999 - 10 31 12 - 1.0 address name description mode (1) default register 1h ? basic status 1.15 100base -t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base - tx full - duplex 1 = capable of 100mbps full - duplex 0 = not capable of 100mbps full - duplex ro 1 1.13 100base - tx half - duplex 1 = capable of 100mbps half - duplex 0 = not capable of 100mbps half - duplex ro 1 1.12 10base -t full - duplex 1 = capable of 10mbps full - duplex 0 = not capable of 10mbps full - duplex ro 1 1.11 10base -t half - duplex 1 = capable of 10mbps half - duplex 0 = not capable of 10mbps half - duplex ro 1 1.10:9 reserved reserved ro 00 1.8 extended status 1 = extended status info in reg. 15h. 0 = no extended status info in reg. 15h. ro 1 1.7 reser ved reserved ro 0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto - negotiation complete 1 = auto - negotiation process completed 0 = auto - negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote faul t ro/lh 0 1.3 auto - negotiation ability 1 = can perform auto - negotiation 0 = cannot perform auto - negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h ? phy identifier 1 2.15:0 phy id number assigned to bits [3:18] of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1h. ro 0022h regi ster 3h ? phy identifier 2 3.15:10 phy id number assigned to bits [19:24] of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1h. ro 0001_01 3.9:4 model number six - bit manufacturer?s model number ro 10_0010 3.3:0 revision number four - bit manufacturer?s revision number ro indicates silicon revision register 4h ? auto - negotiation advertisement 4.15 next page 1 = next page capable 0 = no nex t page capability rw 0
micrel, inc. ksz9031rnx octobe r 2012 44 m9999 - 10 31 12 - 1.0 address name description mode (1) default 4.14 reserved reserved ro 0 4.13 remote fault 1 = remote fa ult supported 0 = no remote fault rw 0 4.12 reserved reserved ro 0 4.11:10 pause [4.11, 4.10] [0,0] = no pause [1,0] = asymmetric pause (link partner) [0,1] = symmetric pause [1,1] = symmetric and asymmetric pause (local device) rw 00 4.9 100bas e -t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability rw 1 4.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability rw 1 4.6 10base -t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability rw 1 4.5 10base -t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 regi ster 5h ? auto - negotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault d etected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 5.11:10 pause [5.11, 5.10] [0,0] = no pause [1,0] = asymmetric p ause (link partner) [0,1] = symmetric pause [1,1] = symmetric and asymmetric pause (local device) rw 00 5.9 100base -t4 1 = t 4 capable 0 = no t4 capability ro 0 5.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability ro 0 5.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability ro 0 5.6 10base -t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability ro 0
micrel, inc. ksz9031rnx octobe r 2012 45 m9999 - 10 31 12 - 1.0 address name description mode (1) default 5.5 10base -t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0000 register 6h ? auto - negotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received ro/lh 0 6.0 link partner auto - negotiation able 1 = link partner has auto - negotiation capability 0 = link partner does not have auto - negotiation capability ro 0 register 7h ? auto - negotiation next page 7.15 next page 1 = additional next pages will foll ow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link cod e word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11- bit wide field to encode 2048 messages rw 000_0000_0001 register 8h ? auto - negotiation link partner next page ability 8.15 next page 1 = additional next pages will follow 0 = last pag e ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = able to act on the information 0 = not able to act on the informat ion ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000
micrel, inc. ksz9031rnx octobe r 2012 46 m9999 - 10 31 12 - 1.0 address name description mode (1) default register 9h ? 1000base - t control 9.15:13 test mode bits transmitter test mode operations [9.15:13] mode [000] normal operation [001] test mode 1 ? transmit waveform test [010] test mode 2 ? transmit jitter test in master mode [011] test mode 3 ? transmit jitter test in slave mode [100] test mode 4 ? transmitter distortion test [101] reserved, operations not identified [110] reserved, operations not identified [111] reserved, operations not identified rw 000 9.12 master - slave manual config uration enable 1 = enable master - slave manua l configuration value 0 = disable master - slave manual configuration value rw 0 9.11 master - slave manual config uration value 1 = configure phy as master during master - slave negotiation 0 = configure phy as slave during master - slave negotiation this bit is ignored if master - slave manual config uration is disabled (reg. 9.12 = 0). rw 0 9.10 port type 1 = indicate the preference to operate as multiport device (master) 0 = indicate the preference to operate as single - port device (slave) this bit is valid only if master - slave m anual config uration is disabled (reg. 9.12 = 0). rw 0 9.9 1000base -t full - duplex 1 = advertise phy is 1000base - t full - duplex capable 0 = advertise phy is not 1000base - t full - duplex capable rw 1 9.8 1000base -t half - duplex 1 = adver tise phy is 1000base - t half - duplex capable 0 = advertise phy is not 1000base - t half - duplex capable rw set by mode[3:0] strapping pins. see the ? strapping options ? section for details. 9.7:0 reserved write as 0, ignore o n read ro ? register ah ? 1000base - t status a.15 master - slave configuration fault 1 = master - slave configuration fault detected 0 = no master - slave configuration fault detected ro/lh/sc 0
micrel, inc. ksz9031rnx octobe r 2012 47 m9999 - 10 31 12 - 1.0 address name description mode (1) default a.14 master - slave configuration resolution 1 = local phy config uration resolved to master 0 = local phy configuration resolved to slave ro 0 a.13 local receiver status 1 = local receiver ok (loc_rcvr_status = 1) 0 = local receiver not ok (loc_rcvr_status = 0) ro 0 a.12 remote receiver status 1 = remote receiver ok (rem_rcvr_status = 1) 0 = remote receiver not ok (rem_rcvr_status = 0) ro 0 a.11 link partner 1000base -t full - duplex capability 1 = link partner is capable of 1000base - t full - duplex 0 = link partner is not capable of 1000base -t full - duplex ro 0 a.10 link partner 1000base -t half - duplex capability 1 = link partner is capable of 1000base - t half - duplex 0 = link partner is not capable of 1000base -t half - duplex ro 0 a.9:8 reserved reserved ro 00 a.7:0 idle error count cumulative count of errors detected when receiver is receiving idles and pma_txmode.indicate = send_n. the counter is incremented every symbol period that rxerror_status = error. ro/sc 0000_0000 register dh ? mmd access ? control d.15:14 mmd ? operation mode for the selected mmd d evice a ddress (bits [4:0] of this register), these two bits select one of the following register or data operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 d.4:0 mmd ? device address the se five bits set the mmd d evice a ddress. rw 0_0000 register eh ? mmd access ? register/data e.15:0 mmd ? register/data for the select ed mmd d evice a ddress (reg. dh, bits [4:0]), when reg. dh, bits [15:14] = 00, this register contains the read/write register address for the mmd de vice address . otherwise, this register contains the read/write data value for the mmd de vice a ddress and its selected r egister a ddress. see also reg. dh, bits [15:14] , for descriptions of post increment reads and writes of this register for data operation. rw 0000_0000_0000_0000
micrel, inc. ksz9031rnx octobe r 2012 48 m9999 - 10 31 12 - 1.0 address name description mode (1) default register fh ? extended status f.15 1000base -x full - duplex 1 = phy can perform 1000 base -x full - duplex 0 = phy can not perform 1000base - x full - duplex ro 0 f.14 1000base -x half - duplex 1 = phy can perform 1000base -x half - duplex 0 = phy cannot perform 1000base -x half - duplex ro 0 f.13 1000base -t full - duplex 1 = phy can perform 1000base -t full - duplex 0 = phy can not perform 1000base -t full - duplex ro 1 f.12 1000base -t half - duplex 1 = phy can perform 1000base -t half - duplex 0 = phy can not perform 1000base -t half - duplex ro 1 f.11:0 reserved ignore when read ro ? note: 1. rw = read/write. ro = read only. sc = self - cleared. lh = latch high. ll = latch low. vendor - specific registers ? descriptions address name description mode (1) default register 11h ? remote loopback 11.15:9 reserved reserved rw 0000_000 11.8 remote loopback 1 = enable r emo te l oopback 0 = disable r emote l oopback rw 0 11.7:1 reserved reserved rw 1111_010 11.0 reserved reserved ro 0 register 12h ? linkmd ? cable diagnostic 12.15 cable diagnostic test enable write value: 1 = enable cable diagnostic test. after test has com pleted, this bit is self - cleared. 0 = disable cable diagnostic test. read value: 1 = cable diagnostic test is in progress. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 12.14 reserv ed this bit should always be set to ?0?. rw 0
micrel, inc. ksz9031rnx octobe r 2012 49 m9999 - 10 31 12 - 1.0 address name description mode (1) default 12.13:12 cable diagnostic test pair these two bits select the differential pair for testing: 00 = differential pair a (pins 2, 3) 01 = differential pair b (pins 5, 6) 10 = differential pair c (pins 7, 8) 11 = differential pair d (pins 10, 11) rw 00 12.11:10 reserved these two bits should always be set to ?00?. rw 00 12.9:8 cable diagnostic status these two bits represent the test result for the selected differential pair in bits [13:12] of this register. 00 = normal cable condition (no fault detected) 01 = open cable fault detected 10 = short cable fault detected 11 = reserved ro 00 12.7:0 cable diagnostic fault data for the open or short cable fault detected in bits [9:8] of this register, this 8 - bit value r epresents the distance to the cable fault. ro 0000_0000 register 13h ? digital pma/pcs status 13.15:3 reserved reserved ro/lh 0000_0000_0000_0 13.2 1000base -t link status 1000base - t link s tatus 1 = link status is ok 0 = link status is not ok ro 0 13.1 100base - tx link status 100base - tx link s tatus 1 = link status is ok 0 = link status is not ok ro 0 13.0 reserved reserved ro 0 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for s ymbol e rror frames ro/rc 0000_0000_0000_0000 re gister 1bh ? interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber i nterrupt 0 = disable jabber i nterrupt rw 0 1b.14 receive error interrupt enable 1 = enable r eceive e rror i nterrupt 0 = disable r eceive e rror i nterrupt rw 0 1b.13 page received interrupt enable 1 = enable p age r eceived i nterrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable p arallel detect fault i nterrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link par tner acknowledge interrupt enable 1 = enable link p artner acknowledge i nterrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link - down interrupt enable 1 = enable l ink -d own i nterrupt 0 = disable l ink - down interrupt rw 0
micrel, inc. ksz9031rnx octobe r 2012 50 m9999 - 10 31 12 - 1.0 address name description mode (1) default 1b.9 remote fault in terrupt enable 1 = enable r emote fault i nterrupt 0 = disable remote fault interrupt rw 0 1b.8 link - up interrupt enable 1 = enable link - up i nterrupt 0 = disa ble link - up i nterrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occur ro/r c 0 1b.6 receive error interrupt 1 = receive e rror occurred 0 = receive error did not occur ro/rc 0 1b.5 page receive interrupt 1 = page r eceive occurred 0 = page r eceive did not occur ro/rc 0 1b.4 parallel detect fault interrupt 1 = parallel d etect f au lt occurred 0 = parall el d etect f ault did not occur ro/rc 0 1b.3 link partner acknowledge interrupt 1 = link p artner a cknowledge occurred 0 = link p art ner acknowledge did not occur ro/rc 0 1b.2 link - down interrupt 1 = link - d own occurred 0 = link - down did not occur ro/rc 0 1b.1 remote fault interrupt 1 = remote f ault occurred 0 = remote fault did not occur ro/rc 0 1b.0 link - up interrupt 1 = link - u p occurred 0 = link - up did not occur ro/rc 0 register 1ch ? auto mdi/mdi - x 1c.15:8 reserved reserved rw 000 0_0000 1c.7 mdi set when swap -o ff (bit [6] of this register) is asserted (1), 1 = ph y is set to operate as mdi mode 0 = phy is set to operate as m di - x mode this bit has no function when swap -o ff is de - asserted (0). rw 0 1c.6 swap -o ff 1 = disable auto md i/mdi - x function 0 = enable auto mdi/mdi - x function rw 0 1c.5:0 reserved reserved rw 00_0000 register 1fh ? phy control 1f.15 reserved reserved rw 0 1f.14 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.13:12 reserve d reserved rw 00 1f.11:10 reserved reserved ro/lh/rc 00 1f.9 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.8:7 reserved reserved rw 00 1f.6 speed s tatus 1000base -t 1 = indicate chip final speed status at 1000base -t ro 0
micrel, inc. ksz9031rnx octobe r 2012 51 m9999 - 10 31 12 - 1.0 address name description mode (1) default 1 f.5 speed s tatus 100base -tx 1 = indicate chip final speed status at 100base -tx ro 0 1f.4 speed s tatus 10base -t 1 = indicate chip final speed status at 10base -t ro 0 1f.3 duplex s tatus indicate chip duplex status 1 = full - duplex 0 = half - duplex ro 0 1f.2 1000base -t ma s ter/slave stat us indicate chip master/s lave status 1 = 10 00base -t m aster mode 0 = 1000base -t s lave mode ro 0 1f.1 reserved reserved rw 0 1f.0 link status check fail 1 = fail 0 = not f ailing ro 0 note: 1. rw = read/write. rc = read - cle ared ro = read only. sc = self - cleared. lh = latch high.
micrel, inc. ksz9031rnx octobe r 2012 52 m9999 - 10 31 12 - 1.0 mmd registers mmd r egisters provide indirect read/write access to up to 32 mmd device addresses with each device supporting up to 65,536 16 - bit registers, as defined in clause 22 of the ieee 802.3 specification. the ksz9031 r nx, however, uses only a small fraction of the available registers. see the ? register map ? section for a list o f supported mmd d evice addresses and their associated r egister a ddresses. the fol lowing two standard r egisters serve as the portal regist ers to access the indirect mmd r egisters. ? standard r egister dh ? mmd access ? control ? standard r egister eh ? mmd access ? register/data address name description mode default register dh ? mmd acces s ? control d.15:14 mmd ? operation mode for the selected mmd device a ddress (bits [4:0] of this register), these two bi ts select one of the following r egister or d ata operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 d.4:0 mmd ? device address the se five bits set the mmd d evice a ddress. rw 0_0000 register eh ? mmd access ? register/data e.15:0 mmd ? register/data for the selected mmd devi ce a ddress (reg. dh, bits [4:0]), when re g. dh, bits [15:14] = 00, this register contains the read/write registe r address for the mmd device address . otherwi se, this regist er contains the read/write d ata value for the mmd d evice a ddress and its selected r egister a ddress. see also reg ister dh, bits [15:14] descriptions for post increment reads and writes of this register for d ata operation. rw 0000_0000_0000_0000 table 18 . portal registers (access to i ndirect mmd registers) examples: ? mmd register write write mmd ? device address 2h, register 10h = 0001h to enable link - up detection to trigger pme for wol. 1. write register dh with 0002h // set up r egis ter a ddress for mmd ? device address 2h. 2. write re gister eh with 0010h // select r egister 10h of mmd ? device address 2h. 3. write register dh with 4002h // select register d ata for mmd ? device address 2h, register 10h. 4. write register eh with 0001h // write v alue 0001h to mmd ? device address 2h, register 10h.
micrel, inc. ksz9031rnx octobe r 2012 53 m9999 - 10 31 12 - 1.0 ? mmd register read read mmd ? device address 2h, register 11h ? 13h for the magic p acket?s mac a ddress 1. write register dh with 0002h // set up register a ddress for mmd ? device address 2h. 2. write register eh with 0011h // select r egister 11h of mmd ? device address 2h. 3. write reg ister dh with 8002h // select re gister d ata for mmd ? device address 2h, register 11h. 4. read register eh // read data in mmd ? device address 2h, register 11h. 5. read register eh // re ad data in mmd ? device address 2h, register 12h. 6. read register eh // read data in mmd ? device address 2h, register 13h. mmd registers ? descriptions address name description mode (1) default mmd address 1h, register 5ah ? 1000base - t link - u p time control 1.5a.15:9 reserved reserved ro 0000_000 1.5a.8:4 reserved reserved rw 1_0000 1.5a.3:1 1000base -t link -u p time when the l ink p artner is another ksz9031 device, the 1000base - t link - up time can be long. these three bits provide an optional setting to redu ce the 1000base - t link - up time. 100 = default power - up setting 011 = optional settin g to reduce link - up time when the link p artner is a ksz9031 device. all other settings are reserved and should not be used. the optional s etting is safe to use with any l ink p artner. note : read/write access to this register bit is available only whe n reg. 0h is set to 0x2100 to disable auto -n egotiation and force 100base - tx mode. rw 100 1.5a.0 reserved reserved rw 0 mmd address 2h, register 0h ? common control 2.0.15:4 r eserved reserved rw 0000_0000_0000 2.0.3 led mode override strap - in for led_mode 1 = single - led m ode 0 = bi - color d ual - led m ode rw set by led_mode strapping pin. see the ? strapping options ? section for details. 2.0.2 res erved reserved rw 0 2.0.1 clk125_en status override strap - in for clk125_en 1 = clk125_en strap - in is enabled 0 = clk125_en strap - in is disabled rw set by clk125_en strapping pin. see the ? strapping options ? section for de tails. 2.0.0 reserved reserved rw 0 mmd address 2h, register 1h ? strap status 2.1.15:8 reserved reserved ro 0000_0000
micrel, inc. ksz9031rnx octobe r 2012 54 m9999 - 10 31 12 - 1.0 address name description mode (1) default 2.1.7 led_mode s trap -i n s tatus strap to 1 = single - led m ode 0 = bi - color dual - led m ode ro set by led_mode strapping pin. see the ? strapping options ? section for details. 2.1.6 reserved reserved ro 0 2.1.5 clk125_en strap -i n s tatus strap to 1 = clk125_en strap - in is enabled 0 = clk125_en strap - in is disabled ro set by clk125_en strapping pin. see the ? strapping options ? section for details. 2.1.4:3 reserved reserved ro 00 2.1.2:0 phyad[2:0] strap - in v alue strap - in value for phy ad dress bits [4:3] of phy a ddress are always set to ?00?. ro set by phyad[2:0] strapping pi n. see the ? strapping options ? section for details. mmd address 2h, register 2h ? operation mode strap override 2.2.15 rgmii all capabilities override 1 = override strap - in for rgmii to advertise all capabilities rw set by mode[3:0] strapping pin. see the ? strapping options ? section for details. 2.2.14 rgmii n o 1000bt_hd o verride 1 = override strap - in for rgmii to advertise all capabilities except 1000base - t half - duplex rw 2.2.13 rgm ii 1000bt_h/fd o nly o verride 1 = override strap - in for rgmii to advertise 1000base - t full - and half - duplex only rw 2.2.12 rgmii 1000bt_fd only o verride 1 = override strap - in for rgmii to advertise 1000base - t full - duplex only rw 2.2.11 reserved reserv ed rw 0 2.2.10 pme_n2 output enable for int_n/pme_n2 (pin 38 ), 1 = enable pme o utput 0 = disable pme o utput this bit works in conjunction with mmd address 2h, reg. 10h, bits [15:14] to define the output for pin 3 8 . rw 0 2.2.9 reserved reserved rw 0 2. 2.8 pme_n1 output enable for led1/pme_n1 (pin 1 7 ), 1 = enable pme o utput 0 = disable pme o utput this bit works in conjunction with mmd address 2h, reg. 10h, bits [15:14] to define the output for pin 17 . rw 0 2.2.7 chip power - down o verride 1 = override strap - in for chip power - down mode rw set by mode[3:0] strapping pin. see the ? strapping options ? section for details. 2.2.6:5 reserved reserved rw 00 2.2.4 nand tree o verride 1 = override strap - in for nand t ree mode rw s et by mode[3:0] strapping pin. see the ? strapping options ? section for details. 2.2.3:0 reserved reserved rw 0000
micrel, inc. ksz9031rnx octobe r 2012 55 m9999 - 10 31 12 - 1.0 address name description mode (1) default mmd address 2h, register 3h ? operation mode strap status 2.3.15 rgmii all capabilities strap - in status 1 = strap to rgmii to advertise all capabilities ro set by mode[3:0] strapping pin. see the ? strapping options ? section for details. 2.3.14 rgmii no 1000bt_hd strap - in status 1 = strap to rgmii to advertise all capabilitie s except 1000base - t half - duplex ro 2.3.13 rgmii only 1000bt_h/fd strap - in status 1 = strap to rgmii to advertise 1000base -t full - and half - duplex only ro 2.3.12 rgmii only 1000bt_fd strap - in status 1 = strap to rgmii to advertise 1000base -t full - dupl ex only ro 2.3.11:8 reserved reserved ro 0000 2.3.7 chip power - down strap - in status 1 = strap to chip power - down mode ro set by mode[3:0] strapping pin. see the ? strapping options ? section for details. 2.3.6:5 reserved reserved ro 00 2.3.4 nand tree strap - in status 1 = strap to nand tree mode ro set by mode[3:0] strapping pin. see the ? strapping options ? section for details. 2.3.3:0 reserved reserved ro 0000 mmd address 2h, register 4h ? r gmii control signal pad skew 2.4.15:8 reserved reserved rw 0000_0000 2.4.7:4 rx_dv pad skew rgmii rx_ctl output pad skew control (0.06ns/step) rw 0111 2.4.3:0 tx_en pad skew rgmii tx_ctl input pad skew control (0.06ns/step) rw 0111 mmd address 2h , register 5h ? rgmii rx data pad skew 2.5.15:12 rxd3 pad skew rgmii rxd3 output pad skew control (0.06ns/step) rw 0111 2.5.11:8 rxd2 pad skew rgmii rxd2 output pad skew control (0.06ns/step) rw 0111 2.5.7:4 rxd1 pad skew rgmii rxd1 output pad skew cont rol (0.06ns/step) rw 0111 2.5.3:0 rxd0 pad skew rgmii rxd0 output pad skew control (0.06ns/step) rw 0111 mmd address 2h, register 6h ? rgmii tx data pad skew 2.6.15:12 txd3 pad skew rgmii txd3 output pad skew control (0.06ns/step) rw 0111 2.6.11:8 txd2 pad skew rgmii txd2 output pad skew control (0.06ns/step) rw 0111 2.6.7:4 txd1 pad skew rgmii txd1 output pad skew control (0.06ns/step) rw 0111 2.6.3:0 txd0 pad skew rgmii txd0 output pad skew control (0.06ns/step) rw 0111
micrel, inc. ksz9031rnx octobe r 2012 56 m9999 - 10 31 12 - 1.0 address name description mode (1) default mmd address 2h, register 8h ? rgmii clock pad skew 2.8.15:10 reserved reserved rw 0000_00 2.8.9:5 gtx_clk pad skew r gmii gtx_clk input pad skew control (0.06ns/step) rw 01_111 2.8.4:0 rx_clk pad skew r gmii rx_clk output pad skew control (0.06ns/step) rw 0_1111 mmd address 2h, r egister 10h ? wake - on - lan ? control 2.10.15:14 pme output select these two bits work in conjunction with mmd address 2h, reg. 2h, bits [8] and [10] for pme_n1 and pme_n2 enable, to define the output for pins 17 and 38 , respectively. led1/pme_n1 (pin 1 7 ) 00 = pme_n1 output only 01 = led1 output only 10 = led1 and pme_n1 output 11 = reserved int_n/pme_n2 (pin 38) 00 = pme_n2 output only 01 = int_n output only 10 = int_n and pme_n2 output 11 = reserved rw 00 2.10.13:7 reserved reserved rw 00_0000_0 2.10.6 magic packet detect enable 1 = enable magic - packet detection 0 = disable magic - packet detection rw 0 2.10.5 custom - packet type 3 detect enable 1 = enable custom - packet, type 3 detection 0 = disable custom - packet, type 3 detection rw 0 2.10.4 custo m - packet type 2 detect enable 1 = enable custom - packet, type 2 detection 0 = disable custom - packet, type 2 detection rw 0 2.10.3 custom - packet type 1 detect enable 1 = enable custom - packet, type 1 detection 0 = disable custom - packet, type 1 detection rw 0 2.10.2 custom - packet type 0 detect enable 1 = enable custom - packet, type 0 detection 0 = disable custom - packet, type 0 detection rw 0 2.10.1 link - down detect enable 1 = enable link - down detection 0 = disable link - down detection rw 0 2.10.0 link - up dete ct enable 1 = enable link - up detection 0 = disable link - up detection rw 0
micrel, inc. ksz9031rnx octobe r 2012 57 m9999 - 10 31 12 - 1.0 address name description mode (1) default mmd address 2h, register 11h ? wake - on - lan ? magic packet, mac -da -0 2.11 .15:0 magic packet mac -da -0 this register stores the lower two bytes of the destination mac address for the magic packet. bit [15:8] = byte 2 (mac address [15:8]) bit [7:0] = byte 1 (mac address [7:0]) the upper four bytes of the destination mac address are stored in the following two registers. rw 0000_0000_0000_0000 mmd address 2h, register 12h ? wake - on - lan ? magic packet, mac - da - 1 2.12.15:0 magic packet mac -da -1 this register stores the middle two bytes of the destination mac address for the magic packet. bit [15:8] = byte 4 (mac address [31:24]) bit [7:0] = byte 3 (mac address [23:16]) the lower two bytes and upper two bytes of the destination mac address are stored in the previous and following registers, respectively. rw 0000_0000_0000_0000 mmd address 2h, register 13h ? wake - on - lan ? magic packet, mac -da -2 2.13.15:0 magic packet mac -da -2 thi s register stores the upper two bytes of the destination mac address for the magic packet. bit [15:8] = byte 6 (mac address [47:40]) bit [7:0] = byte 5 (mac address [39:32]) the lower four bytes of the destination mac address are stored in the previous two registers. rw 0000_0000_0000_0000 mmd address 2h, register 14h ? wake - on - lan ? customized packet, type 0, expected crc 0 mmd address 2h, register 16h ? wake - on - lan ? customized packet, type 1, expected crc 0 mmd address 2h, register 18h ? wake - on - lan ? customized packet, type 2, expected crc 0 mmd address 2h, register 1ah ? wake - on - lan ? customized packet, type 3, expected crc 0 2.14.15:0 2.16.15:0 2.18.15:0 2.1a.15:0 custom packet type x crc 0 this register stores the lower two bytes for the expec ted crc. bit [15:8] = byte 2 (crc [15:8]) bit [7:0] = byte 1 (crc [7:0]) the upper two bytes for the expected crc are stored in the following register. rw 0000_0000_0000_0000 mmd address 2h, register 15h ? wake - on - lan ? customized packet, type 0, expe cted crc 1 mmd address 2h, register 17h ? wake - on - lan ? customized packet, type 1, expected crc 1 mmd address 2h, register 19h ? wake - on - lan ? customized packet, type 2, expected crc 1 mmd address 2h, register 1bh ? wake - on - lan ? customized packet, type 3, expected crc 1 2.15.15:0 2.17.15:0 2.19.15:0 2.1b.15:0 custom packet type x crc 1 this register stores the upper two bytes for the expected crc. bit [15:8] = byte 4 (crc [31:24]) bit [7:0] = byte 3 (crc [23:16]) the lower two bytes for the expected crc are stored in the previous register. rw 0000_0000_0000_0000
micrel, inc. ksz9031rnx octobe r 2012 58 m9999 - 10 31 12 - 1.0 address name description mode (1) default mmd address 2h, register 1ch ? wake - on - lan ? customized packet, type 0, mask 0 mmd address 2h, register 20h ? wake - on - lan ? customized packet, type 1, mask 0 mmd address 2h, register 24h ? w ake- on - lan ? customized packet, type 2, mask 0 mmd address 2h, register 28h ? wake - on - lan ? customized packet, type 3, mask 0 2.1c.15:0 2.20.15:0 2.24.15:0 2.28.15:0 custom packet type x mask 0 this register selects the bytes in the first 16 bytes of th e packet (bytes 1 thru 16) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [15] : byte 1 6 ? : ? bit [2] : byte 2 bit [0] : byte 1 rw 0000_0000_0000_0000 mmd address 2h, register 1dh ? wake - on - lan ? customized packet, type 0, mask 1 mmd address 2h, register 21h ? wake - on - lan ? customized packet, type 1, mask 1 mmd address 2h, register 25h ? w ake- on - lan ? customized packet, type 2, mask 1 mmd address 2h, register 29h ? wake - on - lan ? customized packet, type 3, mask 1 2.1d.15:0 2.21.15:0 2.25.15:0 2.29.15:0 custom packet type x mask 1 this register selects the bytes in the second 16 bytes of the packet (bytes 17 thru 32) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [15] : byt e 32 ? : ? bit [2] : byte 18 bit [0] : byte 17 rw 0000_0000_0000_0000
micrel, inc. ksz9031rnx octobe r 2012 59 m9999 - 10 31 12 - 1.0 address name description mode (1) default mmd address 2h, register 1eh ? wake - on - lan ? customized packet, type 0, mask 2 mmd address 2h, register 22h ? wake - on - lan ? customized packet, type 1, mask 2 mmd address 2h, register 26 h ? wake - on - lan ? customized packet, type 2, mask 2 mmd address 2h, register 2ah ? wake - on - lan ? customized packet, type 3, mask 2 2.1e.15:0 2.22.15:0 2.26.15:0 2.2a.15:0 custom packet type x mask 2 this register selects the bytes in the third 16 bytes of the packet (bytes 33 thru 48) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [15] : byte 48 ? : ? bit [2] : byte 34 bit [0] : byte 33 rw 0000_0000_0000_0000 mmd address 2h, register 1fh ? wake - on - lan ? customized packet, type 0, mask 3 mmd address 2h, register 23h ? wake - on - lan ? customized packet, type 1, mask 3 mmd address 2h, registe r 27h ? wake - on - lan ? customized packet, type 2, mask 3 mmd address 2h, register 2bh ? wake - on - lan ? customized packet, type 3, mask 3 2.1f.15:0 2.23.15:0 2.27.15:0 2.2b.15:0 custom packet type x mask 3 this register selects the bytes in the fourth 16 bytes of the packet (bytes 49 thru 64) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [ 15] : byte 64 ? : ? bit [2] : byte 50 bit [0] : byte 49 rw 0000_0000_0000_0000 mmd address 3h, register 0h ? pcs eee ? control 3.0.15:12 reserved reserved rw 0000 3.0.11 1000base -t force lpi 1 = force 1000base - t low - power idle transmission 0 = normal o peration rw 0 3.0.10 100base - tx rx_clk stoppable during receive lower - power idle mode, 1 = rx_clk stoppable for 100base -tx 0 = rx_clk not stoppable for 100base -tx rw 0 3.0.9:0 reserved reserved rw 00_0000_0000
micrel, inc. ksz9031rnx octobe r 2012 60 m9999 - 10 31 12 - 1.0 address name description mode (1) default mmd address 3h, register 1h ? pcs eee ? st atus 3.1.15:12 reserved reserved ro 0000 3.1.11 transmit low - power idle received 1 = transmit pcs has received low - power idle 0 = low - power idle not received ro/lh 0 3.1.10 receive low - power idle received 1 = receive pcs has received low - power idle 0 = low - power idle not received ro/lh 0 3.1.9 transmit low - power idle indication 1 = transmit pcs is currently receiving low - power idle 0 = transmit pcs is not currently receiving low - power idle ro 3.1.8 receive low - power idle indication 1 = receive pcs i s currently receiving low - power idle 0 = receive pcs is not currently receiving low - power idle ro 3.1.7:0 reserved reserved ro 0000_0000 mmd address 7h, register 3ch ? eee advertisement 7.3c.15:3 reserved reserved rw 0000_0000_0000_0 7.3c.2 1000base -t eee 1 = 1000mbps eee capable 0 = no 1000mbps eee capability this bit is set to ?0? as the default after power -up or reset. set this bit to ?1? to enable 1000mbps eee mode. rw 0 7.3c.1 100base - tx eee 1 = 100mbps eee capable 0 = no 100mbps eee capability this bit is set to ?0? as the default after power -up or reset. set this bit to ?1? to enable 100mbps eee mode. rw 0 7.3c.0 reserved reserved rw 0 mmd address 7h, register 3dh ? eee link partner advertisement 7.3d.15:3 reserved reserved ro 0000_0000_000 0_0 7.3d.2 1000base -t eee 1 = 1000mbps eee capable 0 = no 1000mbps eee capability ro 0 7.3d.1 100base - tx eee 1 = 100mbps eee capable 0 = no 100mbps eee capability ro 0 7.3d.0 reserved reserved ro 0 mmd address 1ch, register 4h ? analog control 4 1c.4. 15:11 reserved reserved rw 0000_0 1c.4.10 10base - te mode 1 = eee 10base - te (1.75v tx amplitude) 0 = standard 10base - t (2.5v tx amplitude) rw 0 1c.4.9:0 reserved reserved rw 00_1111_1111
micrel, inc. ksz9031rnx octobe r 2012 61 m9999 - 10 31 12 - 1.0 address name description mode (1) default mmd address 1ch, register 23h ? edpd control 1c.23.15:1 reserved r eserved rw 0000_0000_0000_000 1c.23.0 edpd mode enable energy - detect power - down mode 1 = enable 0 = disable rw 0 note: 1. rw = read/write. ro = read only. lh = latch high.
micrel, inc. ksz9031rnx octobe r 2012 62 m9999 - 10 31 12 - 1.0 absolute maximum ratings (1) supply voltage (v in ) (dvddl, avddl, avddl_pll) ............. ? 0.5v t o +1.8v (avddh) ................................................. ? 0.5v to +5.0v (dvddh) ................................................. ? 0.5v to +5.0v input voltage (all inputs) .............................. ? 0.5v to +5.0v output voltage (all outputs) ......................... ? 0.5v to +5.0v lead temperature (soldering, 10sec.) ....................... 260c storage temperature (t s ) ......................... ? 55c to +150c operating ratings (2) supply voltage (dvddl, avddl, avddl_pll) ..... +1.140v to +1.260v (avddh @ 3.3v) ............................ +3.135v to +3.465v (avddh @ 2.5v, c - temp only) ....... +2.375v to +2.625v (dvddh @ 3.3v) ............................ +3.135v to +3.465v (dvddh @ 2.5v) ............................ +2.375v to +2.625v (dvddh @ 1.8v) ............................ +1.710v to +1.890v ambient tempe rature (t a commercial: ksz9031r nxc) .............. 0c to +70c (t a industrial: ksz9031r nxi) ................ ? 40c to +85c maximum junction temperature (t j max) ................. 125c thermal resistance ( ja ) .................................... 3 6 . 34 c/w thermal resistance ( jc ) ...................................... 9.47 c/w electrical characteristics ( 3 ) symbol parameter condition min . typ . max . units supply current ? core / digital i/os i core 1.2v total of: dvddl (digital core) + avddl (analog core) + avddl_pll (pll) 10 00base- t link - up (no traffic) 210 ma 1000base - t full - duplex @ 100% utilization 221 ma 100base - tx link - up (no traffic) 63.6 ma 100base - tx full - duplex @ 100% utilization 63.8 ma 10base - t link - up (no traffic) 7.1 ma 10base - t full - dupl ex @ 100% utilization 7.7 ma software power - down mode (reg. 0.11 = 1) 1.0 ma chip power - down m ode (strap - in pins mode[3:0] = 0111 ) 0.7 ma i dvddh_1.8 1.8v for digital i/os (rgmii operating @ 1.8v) 1000base - t link - up (no traffic) 11.2 ma 10 00base- t full - duplex @ 100% utilization 23.6 ma 100base - tx link - up (no traffic) 8.4 ma 100base - tx full - duplex @ 100% utilization 9.8 ma 10base - t link - up (no traffic) 3.6 ma 10base - t full - duplex @ 100% utilization 5.6 ma software po wer - down mode (reg. 0.11 = 1) 5.5 ma chip power - down mode (strap - in pins mode[3:0] = 0111) 0.3 ma notes: 1. exceeding the absolute maximum rating can damage the device. stresses greater than the absolute maximum rating can cause perm anent damage to th e device. operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 2. the device is not guaranteed to functio n outside its operating rating. 3. t a = 25c. specification is for packaged product only.
micrel, inc. ksz9031rnx octobe r 2012 63 m9999 - 10 31 12 - 1.0 symbol parameter condition min . typ . max . units i dvddh_2.5 2.5v for digital i/os (rgmii operating @ 2.5v) 1000base - t link - up (no traffic) 14.7 ma 1000base - t full - duplex @ 100% utilization 31.5 ma 100base -tx link - up (no traffic) 10.5 ma 100base - tx full - duplex @ 100% utilization 13.0 ma 10base - t link - up (no traffic) 6.3 ma 10base - t full - duplex @ 100% utilization 9.0 ma software power - down mode (reg. 0.11 = 1) 6.7 ma chip power - down mode (strap - in pins mode[3:0] = 0111) 0.7 ma i dvddh_3.3 3.3v for digital i/os (rgmii operating @ 3.3v) 1000base - t link - up (no traffic) 19.5 ma 1000base - t full - duplex @ 100% utilization 41.5 ma 100base - tx link - up (no traffic) 13.9 ma 100base - tx full - duplex @ 100% utilization 17.2 ma 10base - t link - up (no traffic) 11.5 ma 10base - t full - duplex @ 100% utilization 13.7 ma software power - down mode (reg. 0.11 = 1) 9.3 ma chip power - down mode (strap - in pins mode[3:0] = 0111) 2.2 ma supply current ? transceiver (equivalent to current draw through external transformer center taps for phy transceivers with current - mode transmit drivers) i avddh_2.5 2.5v for transceiver (recommended for commercial temperature range operation only) 10 00base- t link - up (no traffic) 58.8 ma 1000base - t full - duplex @ 100% utilization 57.9 ma 100base - tx link - up (no traffic) 24.9 ma 100base - tx full - duplex @ 100% utilization 24.9 ma 10base - t link - up (no traffic) 11.5 ma 10base - t full -d uplex @ 100% utilization 25.3 ma software power - down mode (reg. 0h, bit 11 = 1) 3.1 ma chip power - down mode (strap - in pins mode[3:0] = 0111) 0.02 ma i avddh_3.3 3.3v for transceiver 1000base - t link - up (no traffic) 67.4 ma 1000base - t full - duplex @ 100% utilization 66.3 ma 100base - tx link - up (no traffic) 28.7 ma 100base - tx full - duplex @ 100% utilization 28.6 ma 10base - t link - up (no traffic) 15.9 ma 10base - t full - duplex @ 100% utilization 28.6 ma software power - down m ode (reg. 0h, bit 11 = 1) 4.2 ma chip power - down mode (strap - in pins mode[3:0] = 0111) 0.02 ma cmos inputs v ih input high voltage dvddh (digital i/os) = 3.3v 2.0 v dvddh (digital i/os) = 2.5v 1.5 v dvddh (digital i/os) = 1.8v 1.1 v
micrel, inc. ksz9031rnx octobe r 2012 64 m9999 - 10 31 12 - 1.0 symbol parameter condition min . typ . max . units v il input low voltage dvddh (digital i/os) = 3.3v 1.3 v dvddh (digital i/os) = 2.5v 1.0 v dvddh (digital i/os) = 1.8v 0.7 v |i in | input current v in = gnd ~ v ddio 10 a cmos outputs v oh output high voltage dvddh (digital i/os) = 3.3v 2.7 v dvddh (digital i/os) = 2.5v 2.0 v dvddh (digital i/os) = 1.8v 1.5 v v ol output low voltage dvddh (digital i/os) = 3.3v 0.3 v dvddh (digital i/os) = 2.5v 0.3 v dvddh (digital i/os) = 1.8v 0.3 v |i oz | output tri - state leakage 10 a led outputs i led output drive current each led pin (led1, led2) 8 ma pull - up pins pu internal pull - up resistance (mdc, mdio, reset_n pins) dvddh (digital i/os) = 3.3v 13 22 31 k? dvddh (digital i/os) = 2.5v 16 28 39 k? dvddh (digital i/os) = 1.8v 26 44 62 k? 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % output jitter peak -to - peak 0.7 ns 10base - t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak -to - peak 3.5 ns harmonic rejection transmit all - one signal sequence ? 31 db 10base - t receive v sq squelch threshold 5mhz square wave 300 400 mv transmitter ? drive setting v set reference voltage of i set r(i set ) = 12.1k 1.2 v ldo controller ? drive range v ldo_o output drive range for ldo_o (pin 43) to gate input of p- channel mosfet avddh = 3.3v for mosfet source voltage 0.85 2.8 v avddh = 2.5v for mosfet source voltage ( recommended for commercial temperature range operation only) 0.85 2.0 v
micrel, inc. ksz9031rnx octobe r 2012 65 m9999 - 10 31 12 - 1.0 timing diagrams r gmii timing the ksz9031rnx rgmii timing conforms to the timing requirements in the rgmii version 2.0 specification. figure 12 . rgmii v2.0 specification (figure 3 ? multiplexing and timing diagram) timing parameter description min . typ . max . unit tskewt data to c lock output s kew (at t ransmitter) ? 500 500 ps tskewr data to c lock input s kew (at r eceiver) 1.0 2.6 ns tcyc (1000base -t ) clock c ycle d uration for 1000base -t 7.2 8 8.8 ns tcyc (100base - tx) clock c ycle d uration for 100base -tx 36 40 44 ns tcyc (10base -t) clock c ycle d uration for 10base -t 360 400 440 ns table 19. rgmii v2.0 specification (timing sp ecifics from table 2)
micrel, inc. ksz9031rnx octobe r 2012 66 m9999 - 10 31 12 - 1.0 auto - negotiation timing figure 13 . auto - negotiation fast link pulse (flp) timing timing parameter description min . typ . max . units t btb flp bu rst to flp b urst 8 16 24 ms t flpw flp b urst width 2 m s t pw clock/data p ulse width 100 ns t ctd clock pulse to data p ulse 55.5 64 69.5 s t ctc clock pulse to c lock p ulse 111 128 139 s number of c lock/ data pulses per flp b urst 17 33 table 20 . auto - negotiation fast link pulse (flp) timing parameters
micrel, inc. ksz9031rnx octobe r 2012 67 m9999 - 10 31 12 - 1.0 mdc/mdio timing figure 14 . mdc/mdio timing timing parameter description min . typ . max . unit t p mdc period 400 ns t 1md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy inpu t) hold from rising edge of mdc 10 ns t md3 mdio (phy output) delay from rising edge of mdc 0 ns table 21 . mdc/mdio timing parameters
micrel, inc. ksz9031rnx octobe r 2012 68 m9999 - 10 31 12 - 1.0 power - u p/ power - d own/reset timing figure 15 . power -u p/ power - d own/reset timing parameter description min max units t vr supply voltages rise time (must be monotonic) 200 s t sr stable supply voltages to de - assertion of reset 10 ms t cs strap - in pin configuration setup time 5 ns t ch strap - in pin configuration hold time 5 ns t rc de - assertion of reset to strap- in pin output 6 ns t pc supply voltages cycle off -to - on time 150 ms table 22 . power -u p/ power -d own/reset timing parameters note 1 : the recommended power - up sequence is to have the transceiver (avddh) and digital i/o (dvddh) voltages power up before the 1.2v core (dvddl, avddl, avddl_pll) voltage. if the 1.2v core must power up first, the maximum lead time for the 1.2v core voltage with respect to the transceiver and digital i/o voltages should be 200 s. there is no power sequence requirement between transceiver (avddh) and digital i/o (dvddh) power rails. the power - up waveforms should be monotonic for a ll supply voltages to the ksz9031 r nx. note 2 : a fter the de - assertion of rese t, wait a minimum of 100s before starting prog ramming on the miim (mdc/mdio) i nterface. note 3 : the recommended power - down sequence is to have the 1.2v core voltage power down before powering down the transceiver and digital i/o voltages. before the nex t power - up cycle, a ll supply voltages to the ksz9031 r nx should reach 0v and there should be a minimum wait time of 150ms from power - off to power - on.
micrel, inc. ksz9031rnx octobe r 2012 69 m9999 - 10 31 12 - 1.0 reset circuit the following reset circuit is recommended for powering up the ksz9031 r nx if reset is trigge red by the power supply. figure 16 . recommended reset circuit the following reset circuit is recommended for applications where reset is driven by another device ( for example , the cpu or an fpga). at power - on- reset, r, c , a nd d1 provide the necessary ramp rise time to reset the ksz9031 r nx device. the rst_out_n from the cpu/fpga provides the warm reset after power - up. figure 17 . recommended reset circuit for interfacing with cpu/fpga reset output
micrel, inc. ksz9031rnx octobe r 2012 70 m9999 - 10 31 12 - 1.0 reference circuits ? led strap-i n pins the pull - up and pull - down reference circuits for the led2/phyad1 and led1/phyad0 strapping pins are shown in figure 18 for 3.3v and 2.5v dvddh. figure 18 . reference circuits for led strapping pins for 1.8v dvddh, led indication support is not recommended due to the low voltage. without the led indicator, the phyad1 and phyad0 strapping pins are functional with 10 k pull - up to 1.8v dvddh for a value of 1, and with 1.0 k pull - down to ground for a value of 0.
micrel, inc. ksz9031rnx octobe r 2012 71 m9999 - 10 31 12 - 1.0 reference clock ? connection and selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the ksz903 1 r nx. the reference clock is 25 mhz for all operating modes of the ksz9031r nx. figure 19 and table 23 shows the reference clock connection to xi and xo of t he ksz9031r nx, and the reference clock selection cri teria. figure 19 . 25 mhz crystal/oscillator reference clock connection characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm table 23 . reference crystal/clock selection c riteria
micrel, inc. ksz9031rnx octobe r 2012 72 m9999 - 10 31 12 - 1.0 magnetic ? connection and selection a 1:1 isolation transformer is r equired at the line interface. use o ne with integrated common - mode chokes for designs exceeding fcc requirements. an optional auto - transformer stage following the chokes provides additional common - mode noise and signal attenuation. the ksz9031r nx design incorporates voltage - mode transmit drivers and on - chip terminations. with the voltage - mode implementation, the transmit drivers supply the common - mode voltages to the four differe ntial pairs. therefore, the four transformer center tap pins on the ksz9031r nx side should not be connected to any power supply source on the board ; rather, the center tap pins should be separated from one another and connected through separate 0.1 f commo n - mode capacitors to ground. separation is required because the common - mode voltage could be different between the four differential pairs, d epending on the connected speed mode. figure 20 shows the typical gigabit magnetic interface circuit for the ksz9031 r nx. figure 20 . typical gigabit magnetic interface circuit
micrel, inc. ksz9031rnx octobe r 2012 73 m9999 - 10 31 12 - 1.0 table 24 lists recommended magnetic characteristics. parameter value test cond ition turns ratio 1 ct : 1 ct open - circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss (max.) 1.0db 0mhz to 100mhz hipot (min.) 1500vrms table 24 . magnetics selection criteria table 25 is a list of compatible single - port magnetics with separated transformer center tap pins on the g - phy chip side that can be used with the ksz9031 r nx. manufacturer part number auto - t ransformer temperature range magnetic + rj -45 bel fus e 0826- 1g1t -23-f yes 0c to 70c yes halo tg1g - e001nzrl no ? 40c to 85c no halo tg1g - s001nzrl no 0c to 70c no halo tg1g - s002nzrl yes 0c to 70c no pulse h5007nl yes 0c to 70c no pulse h5062nl yes 0c to 70c no pulse hx5008nl yes ? 40c to 85c no pulse jk0654219nl yes 0c to 70c yes pulse jk0 - 0136nl no 0c to 70c yes tdk tla - 7t101lf no 0c to 70c no wurth/midcom 000- 7093- 37r - lf1 yes 0c to 70c no table 25 . compatible single -p ort 10/100/1000 magnetics
micrel, inc. ksz9031rnx octobe r 2012 74 m9999 - 10 31 12 - 1.0 recomme nded land pattern figure 21 . recommended land pattern, 48- pin ( 7 mm x 7 mm) qfn red circle s indicate t hermal v ia s . they should be 0.350 mm in diameter and be connected to the gnd plane for maximum thermal performance. green rec tangle s (with shaded area) indicate solder stencil o pening s on the exposed pad area. they should be 0.93x0.93mm in size, 1.13 mm pitch.
micrel, inc. ksz9031rnx octobe r 2012 75 m9999 - 10 31 12 - 1.0 package information 48- pin (7 mm x 7 mm) qfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in th is data sheet. this information is not i ntended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise , to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authoriz ed for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implan t into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signific ant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2012 micrel, incorporated.

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